similar to: Is subclass of ScheduleDAGMILive a pre-RA scheduler?

Hi, Matthias. >From the class hierarchy, ScheduleDAGMILive is also a ScheduleDAGMI. I am wondering if there will be any problem if we use subclass of ScheduleDAGMILive as post-RA scheduler? The best case is ScheduleDAGMILive just waste time on book-keeping register pressure, but I am not sure if we can still do those book-keeping after RA. Talk about post-RA scheduler, I see there is another

> Please try it out, run tests, build your favourite projects and file > bugs about anything that needs to be fixed, marking them as blockers > of http://llvm.org/pr31622. I have encountered very long compile times for three large source files containing generated/unrolled code at -O1. We are talking about 10+ hours here without completing, so it looks very much like an endless loop. The

Hi, We are currently in the process of upgrading from LLVM 2.9 to LLVM 3.3. We are working on instruction scheduling (mainly for register pressure reduction). I have been following the llvmdev mailing list and have learned that a machine instruction (MI) scheduler has been implemented to replace (or work with?) the selection DAG (SD) scheduler. However, I could not find any document that

I was handed a makefile which is used to compile a library and was told to figure out why the compilation is failing. There is a lot of output and at this point I'm not sure what is important and what is not. I'm trying to solve this problem in small steps, so if asked I can certainly provide more information. The first error that I see during compilation is

On 09/05/2013 18:25, Andrew Trick wrote: > > On May 9, 2013, at 4:02 AM, Fraser Cormack <fraser at codeplay.com > <mailto:fraser at codeplay.com>> wrote: > >> I have an instruction that takes no operands, and produces two >> results, in two consecutive cycles. >> >> I tried both of the following to my Schedule.td file: >> >>

Hey Everyone, I'd like to begin a project to rework the scheduler to address some problems we've discovered on this end. The goal is to get a more configurable/flexible scheduler while simplifying maintenance by separating policy from implementation to get independent and interchangeable parts. This is going to be challenging because we are still stuck on LLVM 2.9. We will be upgrading

Hello. I am using the post-RA (Register Allocation) scheduler to avoid data hazards by inserting other USEFUL instructions from the program (besides NOPs) and it breaks apart some sequences of instructions which should remain "glued" together. More exactly, in my [Target]ISelDAGToDAG.cpp it is possible that I replace for example a BUILD_VECTOR with a machine SDNode called

Sent from my iPhone On Jun 28, 2013, at 2:38 PM, Ghassan Shobaki <ghassan_shobaki at yahoo.com> wrote: > Hi, > > We are currently in the process of upgrading from LLVM 2.9 to LLVM 3.3. We are working on instruction scheduling (mainly for register pressure reduction). I have been following the llvmdev mailing list and have learned that a machine instruction (MI) scheduler has been

On Jun 3, 2013, at 9:42 AM, Steve Montgomery <stephen.montgomery3 at btinternet.com> wrote: > Hi Jakob, > > thanks for the advice. I'll do as you suggest and make sure that CCR is never live. > > I can use pseudo-instructions to bundle cmp+jump but it's not ideal because I might also have to bundle cmp+jump+jump+... into a pseudo. Also, there are several flavours of

Thanks  Kryzstof, I will look at it. Is there any class that I should look at it ? What about Dataflow.h ? Since I am kind of new, I want to know which classes can help me quicker.    =========================================== Phone : 82-42-860-1838 Fax : 82-42-860-6790 Cell Phone: 82-10-7599-1981 =========================================== --- On Sat, 11/3/12, Krzysztof Parzyszek

Dear Raul, Instruction selection and instruction scheduling is, to the best of my knowledge, done at the MachineInstr (MI) IR level. The documentation you've read is on the target independent LLVM IR. You will probably need to read the documentation on LLVM's code generator. The documents on Writing an LLVM Backend, the LLVM Target Independent Code Generator, and Machine IR Format

On Apr 20, 2012, at 10:31 AM, dag at cray.com wrote: > I'd like to begin a project to rework the scheduler to address some > problems we've discovered on this end. The goal is to get a more > configurable/flexible scheduler while simplifying maintenance by > separating policy from implementation to get independent and > interchangeable parts. > > This is going to be

Hello All, I would like your help to learn how to traverse an LLVM DAG and perform some analysis. I know that llc can be used to view a DAG, but I would like to manipulate them. In particular I'm interested in the instruction selection and the scheduling DAGs. I have read the documentation about writing an analysis pass and I know how to traverse a basic block on a LLVM IR assembly file, but

Thanks for the suggestion. I tried your fix. It worked for my particular case, but then I got a following error: clang-3.5: /home/rail/projects/escala_llvm/trunk/llvm-or1k/lib/CodeGen/RegisterPressure.cpp:39: void decreaseSetPressure(std::vector<unsigned int>&, llvm::PSetIterator): Assertion `CurrSetPressure[*PSetI] >= Weight && "register pressure underflow"'

I see that there are several options to influence instruction scheduling, but there doesn't seem to be a lot of information about what they do, for example: -misched-topdown -misched-bottomup The description in MachineScheduler.cpp says: "Force top-down list scheduling" and "Force bottom-up list scheduling" Which isn't too helpful - where might I want to use these?

I think those should be considered internal options for (llvm codegen) developers, a normal compiler user should not need to use any of them. Of course you can look around the llvm sourcecode (esp. in lib/CodeGen/MachineScheduler.cpp) and see what cl::opt options are available and how they affect the scheduler operation. In case of the MachineScheduler all settings are the same regardless of the

I am working on a project where we are integrating an existing pre-RA scheduler into LLVM and we are trying to match our peak register pressure values with the machine instruction schedulers values while using X86. I am finding some mismatches in test cases like the one attached. The registers "AH" and "AL" are live-out but not live-in and I don't see that they are defined

Thank you for the answers! We are currently trying to test the MI scheduler. We are using LLVM 3.3 with Dragon Egg 3.3 on an x86-64 machine. So far, we have run one SPEC CPU2006 test with the MI scheduler enabled using the option -fplugin-arg-dragonegg-llvm-option='-enable-misched:true' with -O3. This enables the machine scheduler in addition to the SD scheduler. We have verified this by

Hi Jakob, thanks for the advice. I'll do as you suggest and make sure that CCR is never live. I can use pseudo-instructions to bundle cmp+jump but it's not ideal because I might also have to bundle cmp+jump+jump+... into a pseudo. Also, there are several flavours of cmp instruction so I might need a lot of pseudos. That's what led me to wonder whether MachineInstrBundles might be a

Also you might need to check use PostRASchedulerList or PostMachineScheduler, PostRASchedulerList is considered deprecated as mentioned in [1]. [1] http://lists.llvm.org/pipermail/llvm-dev/2017-April/112348.html HTH, chenwj 2017-06-10 4:03 GMT+08:00 陳韋任 <chenwj.cs97g at g2.nctu.edu.tw>: > Not saying I am totally understand how thing works, but I think you're > misleading >