similar to: LoopVectorizer with ifconversion

On 17 March 2017 at 16:34, Hal Finkel <hfinkel at anl.gov> wrote: > In general, this is true everywhere. In a large vectorized loop, this cost > may well be worthwhile. The idea is that the cost model should account for > all of these costs. If it doesn't properly, we should fix that. Isn't this only worth when the SIMD instructions can be conditionalised per lane? I

Hi, I have been discussing a bit with Sanjay on how to handle the poor sequences of shufflevector instructions produced by the loop vectorizer and he suggested we bring this up on llvm-dev. I have run into this in the past also and it surprised me to again see (on SystemZ) that the vectorized loop did many seemingly unnecessary shuffles. In this case (see

On 07/24/2018 02:58 AM, Nema, Ashutosh wrote: > >   > >   > > *From:*Hal Finkel <hfinkel at anl.gov> > *Sent:* Tuesday, July 24, 2018 5:05 AM > *To:* Craig Topper <craig.topper at gmail.com>; hideki.saito at intel.com; > estotzer at ti.com; Nemanja Ivanovic <nemanja.i.ibm at gmail.com>; Adam > Nemet <anemet at apple.com>; graham.hunter at

Hi, I am a little unsure about the semantics of the ShuffleKind SK_ExtractSubvector. It seems a subvector is to be extracted, starting from a given index of a given subtype. First of all, if index 0 is passed, I suppose this would mean a noop? But what about calls like the one made of LoopVectorizer for Instruction::PHI in getInstructionCost(): return

Hi, Can the tools in LLVM create a Win32 exe or dll file? Or does LLVM still rely on Binutils and GCC for that? Is it possible/feasable/wanted that the LLVM toolchain could do this? Thanks, Ruben

Hello all, I''m having a bit of an internal conflict here. I have a web application that I need to write (for myself). Fine, right? Well, this site is for a DNS service that has a client interface for client APIs to access. I''d like to have all application requests and data updates/retrieval to go through this interface instead of a database. Should I even use Rails for

On Tue, Oct 10, 2017 at 4:48 PM, Friedman, Eli via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 10/9/2017 3:10 AM, Gaël Jobin via llvm-dev wrote: > > Hi all, > > I got a silly bug when compiling our project with the latest Clang. Here's > the outputted assembly: > > tst r3, #255 > strbeq r6, [r7] > ldreq r6, [r4, r6, lsl #2] > strne r6, [r7, #4]

Hello, I have a few questions about applying the IfConversion pass to my out-of-tree target. (1) Is it true that the IfConversion pass may only run after register allocation? I often encounter this bad scenario, and I think it could be entirely avoided if IfConversion ran before register allocation: the block-to-be-predicated contains load-immediate (LI) instructions. The LI instructions

Hi all, I have just upgraded to a new satellite internet provider. I have two network cards - one with a public IP connected to my satellite router, and the second network card with private IP into my switch for the LAN. Shorewall firewall My old satellite system is not being used. Would it be possible/feasable to install a third network card into my Fedora Core 2 server, and then direct all

Hi All, How can I run the IfConversion pass in JIT to optimize my code for ARM as a Target Architecture? -- View this message in context: http://llvm.1065342.n5.nabble.com/Machine-level-IfConversion-for-ARM-tp69513.html Sent from the LLVM - Dev mailing list archive at Nabble.com.

Assume an architecture that has multiple condition code registers, e.g., powerpc. Now assume that there are predicate instructions like thumb2, but can specify which condition code register they refer to. Now also assume that these predicate instructions themselves are predicatible, if executed they change the current predication state. Can LLVM handle multiple levels of predication? When is

Hi all, I am using llvm backend to generate binary for a specific accelerator. I would like to convert instructions into predicated form when instructions are still in SSA form. It looks like that ifconversion execution flow is different when instructions are in SSA form. However, I am encountering many problems (specially with registers) when I use it before register allocation. I was wondering

Hello! The if-converter tries to match 'Simple' patterns looking like this: // Simple (split, no rejoin): // EBB // | \_ // | | // | TBB---> exit // | // FBB The IfConverter::ValidSimple method (lib/CodeGen/IfConversion.cpp:461) checks if TBB matches this pattern. It basically does this by simply checking if AnalyseBranch fails on

Hi. On our system we have a problems with recursive IfConversion algorithm. Here is the patch for making it loop-based. Or do I need to send it to some other mail-list? -- Best regards, Andrew Zhogin. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130701/f526e1f0/attachment.html> -------------- next

----- Original Message ----- > From: "Pekka Jääskeläinen" <pekka.jaaskelainen at tut.fi> > To: "Hal Finkel" <hfinkel at anl.gov> > Cc: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu>, "Nadav Rotem" <nrotem at apple.com> > Sent: Friday, January 25, 2013 8:14:57 AM > Subject: Re: [LLVMdev] LoopVectorizer in OpenCL

Hi, I am trying to implement support for an if-conversion pass in a backend for the ADRES CGRA architecture. >From studying the existing IfConversion pass, I observed the following: - The PredicateInstruction method is meant to insert guards into conditional instructions. - This method assumes that one will be able to get the predicate from the conditional branch instruction on which

I need to do some analysis, in which I have to selectively convert IFs. I am trying to find a way to call this optimization pass from the JIT code, thus I can decide which branches to convert and which to keep. Apparently I cannot do this using a pass manager. -- View this message in context: http://llvm.1065342.n5.nabble.com/Machine-level-IfConversion-for-ARM-tp69513p69622.html Sent from the

Hi all, I got a silly bug when compiling our project with the latest Clang. Here's the outputted assembly: > tst r3, #255 > strbeq r6, [r7] > ldreq r6, [r4, r6, lsl #2] > strne r6, [r7, #4] > ldr r6, [r4, r6, lsl #2] > bx r6 For the code to execute correctly, either the _ldr_ should be a _ldrne_ instruction or the _ldreq_ instruction should be removed. The error seems to

----- Original Message ----- > From: "Pekka Jääskeläinen" <pekka.jaaskelainen at tut.fi> > To: "Nadav Rotem" <nrotem at apple.com> > Cc: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu> > Sent: Friday, January 25, 2013 5:35:16 AM > Subject: Re: [LLVMdev] LoopVectorizer in OpenCL C work group autovectorization > > On

----- Original Message ----- > From: "Pekka Jääskeläinen" <pekka.jaaskelainen at tut.fi> > To: "Ralf Karrenberg" <Chareos at gmx.de> > Cc: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu> > Sent: Thursday, January 31, 2013 11:15:43 AM > Subject: Re: [LLVMdev] LoopVectorizer in OpenCL C work group autovectorization > > Hi