Displaying 20 results from an estimated 10000 matches similar to: "Why ISel Shifts operations can only be expanded for Value type vector ?"
2017 Mar 04
7
Why ISel Shifts operations can only be expanded for Value type vector ?
On Saturday, March 4, 2017, Ryan Taylor <ryta1203 at gmail.com> wrote:
> Why you can't still expand it through MUL with a Custom lowering? Or am I
> missing something?
>
> Yes we can but problem occurs when we know that it is shift with constant
value than if we return ISD::MUL with constant imm operand than LLVM will
convert it to SHL again because the constant will be
2017 Mar 04
2
Why ISel Shifts operations can only be expanded for Value type vector ?
On Sat, Mar 4, 2017 at 1:19 PM, Bruce Hoult <bruce at hoult.org> wrote:
> If your target does not have SHL then why don't you simply disable
> converting MUL to SHL?
>
> MUL is converted to SHL by target independent passes when second operand
is power of 2.
-Vivek
>
> On Sat, Mar 4, 2017 at 8:22 AM, vivek pandya via llvm-dev <
> llvm-dev at lists.llvm.org>
2018 Dec 13
2
Dealing with information loss for widened integer operations at ISel time
As previously discussed in an RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, the
RISC-V backend has i64 as the only legal integer type for the RV64 target.
Thanks to variable-sized register class support, this means there is no need
for duplication of either patterns or instruction definitions for RV32 and
RV64. It's worth noting that RV64I is a different base
2017 May 15
2
Disabling DAGCombine's specific optimization
Hello LLVM Developers,
I am working on an architecture which have one bit shift operation if
barrel shiftier hardware is not present in such cases some DAGCombine
optimizations reduces performance of certain benchmarks upto 5% for example
consider follwing optimization:
fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
Here it introduce 2 shift operations and when barrel
2012 Jan 07
2
[LLVMdev] libcalls for shifts
Hello,
my target has libcall support for long long shifts. I already have the
following lines in my Lowering constructor:
setLibcallName(RTLIB::SHL_I64, "__llshl");
setLibcallName(RTLIB::SRL_I64, "__llshru");
setLibcallName(RTLIB::SRA_I64, "__llshr");
and
setOperationAction(ISD::SHL, MVT::i64, Expand);
setOperationAction(ISD::SRA, MVT::i64,
2009 Apr 20
1
[LLVMdev] How to prevent LLVM from undoing a custom lowering
My target has only logical shifts and lacks an arithmetic right shift
instruction.
I have a custom LowerSRA function that rewrites SRA as SHL + SIGN_EXTEND
when the shift width is either constant 16 or 24. Unfortunately, I
observe that a
later pass combines the SHL + SIGN_EXTEND back into SRA so we crash.
The idea I had for defeating this behavior is lower to a target-specific
version of SHL
2012 Jan 08
4
[LLVMdev] libcalls for shifts
> Is i64 a legal type on your target? If so, you might need to hack the
> code generator a bit; no in-tree target has a legal integer type that
> doesn't support shifts. If not, I have no idea how you're getting
> that error.
Yes, well, i64 is a legal type, that's how it is. However, i64s are
always stored in two 32-bit registers and in some cases need complicated
2015 May 28
1
[LLVMdev] [ARM backend] adding pattern for SMLALBB
Hi James/Tim,
I am trying to add a patterns for SMLALBB
I think these two assembly patterns can be reduced to SMLALBB using tablegen.
1)
smulbb r2, r3, r2
adds r0, r2, r0 (RdLo)
asr r3, r2, #31
adc r1, r3, r1 (RdHi) ==> smlalbb r0, r1, r3, r2
I have added pattern in def SMLALBB : AMulxyI64< ..... as below :-
[] modified to ---> [((set GPR:$RdLo,
2009 Dec 01
4
[LLVMdev] Possible bug in ExpandShiftWithUnknownAmountBit
Hello,
I'm working in adding support for 64-bit integers to my target. I'm using
LLVM to decompose the 64-bit integer operations by using 32-bit registers
wherever possible and emulating support where not. When looking at the bit
shift decomposition I saw what seems to be a bug in the implementation. The
affected function is ExpandShiftWithUnknownAmountBit in
LegalizeIntegerTypes.cpp.
2017 Feb 27
2
When AVR backend generates mulsu instruction ?
Thanks Dylan,
I am working on a backend which has mulhsu instruction that performs
multiplication between signed and unsigned number and returns upper 32 bits
into result register. I think I also need to write some code probably as
you indicated to check signedness of the operands and based on that lower
to mulhsu instruction.
-Vivek
On Mon, Feb 27, 2017 at 11:13 AM, Dylan McKay <me at
2020 May 12
2
BPF tablegen+codegen question
In BPF, an ADD instruction is defined as a 2 register instruction:
0x0f. add dst, src. dst += src
In BPFInstrInfo.td this kind of ALU instruction is defined with:
def _rr : ALU_RR<BPF_ALU64, Opc,
(outs GPR:$dst),
(ins GPR:$src2, GPR:$src),
"$dst "#OpcodeStr#" $src",
[(set
2017 May 15
2
Disabling DAGCombine's specific optimization
Hi Vivek,
You could work around this by creating a custom ISD node, e.g.
MyTargetISD::MyLSHR, with the same type as the general ISD::LSHR. This
custom node will then be ignored by the generic DAGCombiner. Convert
ISD::LSHR to MyTargetISD::MyLSHR in DAGCombine, optimise it as you see fit,
convert it back or lower it directly.
I've done this for ISD::CONCAT_VECTORS to avoid an inconvenient
2018 Dec 14
2
Dealing with information loss for widened integer operations at ISel time
On Thu, 13 Dec 2018 at 21:41, Friedman, Eli <efriedma at codeaurora.org> wrote:
>
> On 12/13/2018 6:25 AM, Alex Bradbury wrote:
> > There's also likely to be cases where you want to calculate the demanded bits
> > in order to determine if e.g. a W-suffixed instruction can be selected for
> > `(somoeop (zexti32 GPR:$rs1), (zexti32 GPR:$rs2))`. This is easy to match
2012 Jan 10
0
[LLVMdev] libcalls for shifts
Johannes,
Try a custom lowering of the 64bit shift instructions and then in the Lower[SRL|SHL|SRA] function, generate a call instruction to the function you want.
Micah
> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
> On Behalf Of Johannes Birgmeier
> Sent: Sunday, January 08, 2012 2:38 AM
> To: llvmdev at cs.uiuc.edu
2016 Nov 08
2
RFC: Killing undef and spreading poison
Hi Nuno, Chandler,
Nuno Lopes via llvm-dev wrote:
> This program stores 8 bits, and leaves the remaining 24 bits
> uninitialized. It then loads 16 bits, half initialized to %v, half
> uninitialized. SROA transforms the above function to:
>
> define i16 @g(i8 %in) {
> %v = add nsw i8 127, %in
> %1 = zext i8 %v to i16
> %2 = shl i16 %1, 8
> %3 = and
2017 Feb 26
2
When AVR backend generates mulsu instruction ?
Hello LLVMDevs,
I am looking for an example for how to lower LLVM IR to mulsu kind of
instruction. I found that AVR back end have such instruction but
AVRInstrInfo.td does not define any DAG pattern for which this
instruction gets emitted.
def MULSURdRr : FMUL2RdRr<1,
(outs),
(ins GPR8:$lhs, GPR8:$rhs),
"mulsu\t$lhs, $rhs",
[]>,
Requires<[SupportsMultiplication]>;
Also
2019 Jun 10
2
Bug: Library functions for ISD::SRA, ISD::SHL, and ISD::SRL
LLVM appears to support Library functions for ISD::SRA ,ISD::SHL, and ISD::SRL, as they are properly defined in RuntimeLibCalls.def.
The library functions defined in RuntimeLibCalls.def (among others) are these:
HANDLE_LIBCALL(SRA_I16, "__ashrhi3")
HANDLE_LIBCALL(SRA_I32, "__ashrsi3")
HANDLE_LIBCALL(SRA_I64, "__ashrdi3")
However, setting
2016 Nov 09
4
RFC: Killing undef and spreading poison
> On 11/8/2016 3:32 PM, Sanjoy Das wrote:
>> Hi Nuno, Chandler,
>>
>> Nuno Lopes via llvm-dev wrote:
>> > This program stores 8 bits, and leaves the remaining 24 bits
>> > uninitialized. It then loads 16 bits, half initialized to %v, half
>> > uninitialized. SROA transforms the above function to:
>> >
>> > define i16 @g(i8 %in) {
2019 Jun 10
2
Bug: Library functions for ISD::SRA, ISD::SHL, and ISD::SRL
Hi Eli,
Thanks for pointing to the CTLZ_ZERO_UNDEF “LibCall” implementation. I have not it in the version that I am currently using, so it’s nice to know that it’s implemented now.
Incidentally, the CTLZ… implementation is IDENTICAL to what I am proposing for the Shifts. This is not just adding support for “out-of-tree-targets”, but giving consistency to the fact that we have perfectly defined
2017 Sep 22
2
[Hexagon] Type Legalization
Is VT a legal type on Hexagon? It looks like Hexagon may be setting SHL as
Custom for every defined vector type. Try adding TLI.isTypeLegal(VT) too.
~Craig
On Thu, Sep 21, 2017 at 10:06 PM, Haidl, Michael <
michael.haidl at uni-muenster.de> wrote:
> Hi Sanjay,
>
> thanks for this information. I did get a little bit further with the
> patch. However, Hexagon gives me headaches.