similar to: clang/llvm support for %= in inline assembly

Displaying 20 results from an estimated 200 matches similar to: "clang/llvm support for %= in inline assembly"

2017 Feb 05
2
clang/llvm support for %= in inline assembly
I encountered this issue of unique asm label names just now, in https://bugs.freebsd.org/216771 . A very simple test case is this: void foo(void) { asm volatile( "named_label:\n" "jnz named_label\n" ); } void bar(void) { foo(); } Compiling this with any form of optimization gives an error, because clang is attempting to inline foo() into
2013 Mar 04
2
[LLVMdev] [MIPS] How can I add a constraint to LLVM/Clang for MIPS BE?
Hi Jack, On Sat, Mar 2, 2013 at 8:15 AM, Jack Carter <Jack.Carter at imgtec.com> wrote: > Jia, > > I made what I believe to be the correct changes and rebuilt clang and llc. Are the results what you expected? I so I will prepare the patches for commitment. > > Jack > > clang ../mips_R_JiaLiu.c -o mips_R_JiaLiu.ll -emit-llvm -O3 -S -target mipsel-unknown-linux -std=gnu89
2013 Mar 05
0
[LLVMdev] [MIPS] How can I add a constraint to LLVM/Clang for MIPS BE?
Maybe try: .set noat AT is needed to create certain instructions from pseudo instructions, so you have to be careful how you use this. Some instructions that you can use in Mips assembler are in fact pseudos. While AT is not available to it (.set noat), the assembler can not assemble certain pseudos for you. On 03/03/2013 06:02 PM, Jia Liu wrote: > Hi Jack, > > On Sat, Mar 2, 2013
2010 Dec 06
2
[LLVMdev] disable llc optimizations
On Dec 6, 2010, at 10:57 AM, John Criswell wrote: > On 12/6/10 11:39 AM, Andrew Lukefahr wrote: >> Hi, >> >> How would I disable dead code elimination in llc? Can that be done via the command line or do I need to modify llc's source? > > You can use llc --help-hidden to see a list of options. There are several -disable-xxx options that disable various code
2020 Jan 07
2
Inline assembly in intel syntax mishandling i constraint
Hi all, I'm getting rather odd behavior from a call asm inteldialect(). TL;DR is "mov reg, $0" with a "i" constraint on $0 is behaving identical to "mov reg, dword ptr [$0]" and differently from "movl $0, reg" in AT&T syntax. I'm not sure how to get clang to emit an inteldialect, so for this example, I'm emitting llvm and then modifying
2017 Aug 21
3
DragonEgg for GCC v8.x and LLVM v6.x is just able to work
Hi LLVM and GCC developers, My sincere thanks will goto: * Duncan, the core developer of llvm-gcc and dragonegg http://llvm.org/devmtg/2009-10/Sands_LLVMGCCPlugin.pdf * David, the innovator and developer of GCC https://dmalcolm.fedorapeople.org/gcc/global-state/requirements.html and others who give me kind response for teaching me patiently and carefully about how to migrate GCC v4.8.x to
2020 Jan 08
2
Inline assembly in intel syntax mishandling i constraint
> On Jan 7, 2020, at 18:41, Craig Topper <craig.topper at gmail.com> wrote: > > What version of llvm are you using? This looks like it may be fixed on trunk. After poking at my installation of rust, I'm not entirely sure what version of LLVM it uses. Looking at the GitHub page, it looks like Rust maintains their own copy of llvm and cherry picks commits. The C example was
2010 Dec 07
0
[LLVMdev] disable llc optimizations
Ok, I'm trying to get llvm to decide when to turn the multiplier "on" and "off" for an ARM simulator. These instructions are just to let the simulator know when to power on/off the multiplier. I need to insert an instruction before the first multiply and another one after the last multiply in a basic block. I'm currently trying to figure out the best way to do that
2013 May 16
2
[LLVMdev] #APP/#NOAPP
On 05/15/2013 10:53 PM, Richard Smith wrote: > On Mon, May 6, 2013 at 9:09 AM, reed kotler <rkotler at mips.com > <mailto:rkotler at mips.com>> wrote: > > On 05/06/2013 08:51 AM, Rafael Espíndola wrote: > > It's working fine just that it's ugly to see those > APP/NOAPP markers. > > Inline assembly is inline
2017 May 02
4
[ARM/Thumb] Make a function in arm while in Thumb triple
Hi, I wanted to know if it was possible to force ARM backend to compile a function in ARM while the rest is in Thumb mode. I tried the attributes which is used in GCC but it doesn't work. Here is what I tried: https://pastebin.com/jCr5LPUY Thanks in advance, Uvekilledkenny -------------- next part -------------- An HTML attachment was scrubbed... URL:
2014 Feb 20
3
[LLVMdev] [LLVM] Forward temp label references on ARM in LDR with .ltorg in inline assembly are broken in trunk
I'm not entirely sure what caused this, but the following code, which used to behave as expected, is now broken: ---- lolwut.c ---------------------------- void lolwut(void) { __asm __volatile ( "ldr r1, =1f \n" ".ltorg \n" "1: \n\t" : : : "r0", "r1" ); } ------------------------------------------- ~/clang
2013 May 16
0
[LLVMdev] #APP/#NOAPP
On Thu, May 16, 2013 at 3:17 AM, reed kotler <rkotler at mips.com> wrote: > On 05/15/2013 10:53 PM, Richard Smith wrote: > > On Mon, May 6, 2013 at 9:09 AM, reed kotler <rkotler at mips.com> wrote: >> >> On 05/06/2013 08:51 AM, Rafael Espíndola wrote: >>>> >>>> It's working fine just that it's ugly to see those APP/NOAPP markers.
2013 May 16
1
[LLVMdev] #APP/#NOAPP
On 05/16/2013 10:06 AM, Eric Christopher wrote: > On Thu, May 16, 2013 at 3:17 AM, reed kotler <rkotler at mips.com> wrote: >> On 05/15/2013 10:53 PM, Richard Smith wrote: >> >> On Mon, May 6, 2013 at 9:09 AM, reed kotler <rkotler at mips.com> wrote: >>> On 05/06/2013 08:51 AM, Rafael Espíndola wrote: >>>>> It's working fine just that
2019 May 13
3
How to change CLang struct alignment behaviour?
Hi Joan, On Mon, 13 May 2019 at 18:01, Joan Lluch <joan.lluch at icloud.com> wrote: > After looking at it a bit further, I think this is a Clang thing. Clang issues “align 2” if the struct has at least one int (2 bytes), but also if the entire struct size is multiple of 2. For example a struct with 4 char members. In these cases the LLVM backend correctly creates word sized load/stores
2020 Aug 05
10
[RFC] Machine Function Splitter - Split out cold blocks from machine functions using profile data
Greetings, We present “Machine Function Splitter”, a codegen optimization pass which splits functions into hot and cold parts. This pass leverages the basic block sections feature recently introduced in LLVM from the Propeller project. The pass targets functions with profile coverage, identifies cold blocks and moves them to a separate section. The linker groups all cold blocks across functions
2013 May 16
0
[LLVMdev] #APP/#NOAPP
On Mon, May 6, 2013 at 9:09 AM, reed kotler <rkotler at mips.com> wrote: > On 05/06/2013 08:51 AM, Rafael Espíndola wrote: > >> It's working fine just that it's ugly to see those APP/NOAPP markers. >>> >> Inline assembly is inline assembly. It has the semantics defined in >> the IL documentation and should all be treated uniformly. >> >>
2012 Jul 11
4
[LLVMdev] A problem with inline assembly in llvmc for ARM
Hi, I encountered an issue with inline assembly in my c files compiled with llvmc. When I have a push instruction in the inline assembly like: __asm__ volatile ( "push {r4}\n\t" ); the compiler will drop the curly braces and leave it in the generated assembly file as: push r4 And this is non-conformant with the ARM
2018 Oct 10
5
PROPOSAL: Extend inline asm syntax with size spec
On Wed, Oct 10, 2018 at 01:54:33PM -0500, Segher Boessenkool wrote: > It would be great to hear from kernel people if it works adequately for > what you guys want it for :-) Sure, ping me when you have the final version and I'll try to build gcc with it and do some size comparisons. Thx. -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the
2018 Oct 10
5
PROPOSAL: Extend inline asm syntax with size spec
On Wed, Oct 10, 2018 at 01:54:33PM -0500, Segher Boessenkool wrote: > It would be great to hear from kernel people if it works adequately for > what you guys want it for :-) Sure, ping me when you have the final version and I'll try to build gcc with it and do some size comparisons. Thx. -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the
2020 Jun 22
3
Hardware ASan Generating Unknown Instruction
Hi, I am trying to execute a simple hello world program compiled like so: path/to/compiled/clang -o test --target=aarch64-linux-gnu -march=armv8.5-a -fsanitize=hwaddress --sysroot=/usr/aarch64-linux-gnu/ -L/usr/lib/gcc/aarch64-linux-gnu/10.1.0/ -g test.c However, when I look at the disassembly, there is an unknown instruction listed at 0x2d51c: 000000000002d4c0 main: 2d4c0: ff c3 00 d1