Displaying 20 results from an estimated 30000 matches similar to: "how to verify completeness of the llvm backend"
2016 May 11
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
----- Original Message -----
> From: "vivek pandya" <vivekvpandya at gmail.com>
> To: "Matthias Braun" <matze at braunis.de>
> Cc: "Hal Finkel" <hfinkel at anl.gov>, "llvm-dev"
> <llvm-dev at lists.llvm.org>
> Sent: Wednesday, May 11, 2016 1:14:07 PM
> Subject: Re: [llvm-dev] [GSoC 2016] Interprocedural Register
2016 May 25
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
On Wed, May 25, 2016 at 3:53 AM, Hal Finkel <hfinkel at anl.gov> wrote:
>
> ------------------------------
>
> *From: *"vivek pandya" <vivekvpandya at gmail.com>
> *To: *"Quentin Colombet" <qcolombet at apple.com>
> *Cc: *"Hal Finkel" <hfinkel at anl.gov>, "llvm-dev" <llvm-dev at lists.llvm.org>,
>
2016 May 25
3
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
> On May 24, 2016, at 10:08 PM, vivek pandya <vivekvpandya at gmail.com> wrote:
>
>
>
> On Wed, May 25, 2016 at 10:08 AM, Mehdi Amini <mehdi.amini at apple.com <mailto:mehdi.amini at apple.com>> wrote:
>
>> On May 24, 2016, at 9:17 PM, vivek pandya <vivekvpandya at gmail.com <mailto:vivekvpandya at gmail.com>> wrote:
>>
>> Dear
2016 May 25
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
On Wed, May 25, 2016 at 8:44 AM, Hal Finkel <hfinkel at anl.gov> wrote:
>
> ------------------------------
>
> *From: *"vivek pandya" <vivekvpandya at gmail.com>
> *To: *"Hal Finkel" <hfinkel at anl.gov>
> *Cc: *"llvm-dev" <llvm-dev at lists.llvm.org>, "Matthias Braun" <
> matze at braunis.de>, "Mehdi
2017 May 05
2
Idea for Open Project : Smarter way of dumping LLVM IR with -emit-after-all
> On May 5, 2017, at 8:49 AM, Hal Finkel <hfinkel at anl.gov> wrote:
>
>
>
> On 05/05/2017 10:44 AM, vivek pandya via llvm-dev wrote:
>> Hello LLVM Devs,
>>
>> I have an idea to improve effectiveness of IR dump with -emit-after-all based on Adam Nemet's 2016 LLVM Dev presentation.
>> I think we can track changes in each function, basic block and
2016 May 24
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
Hello,
I have written following code to check each register if it is used by
machineFunction or not :
MachineRegisterInfo *MRI = &MF.getRegInfo();
TargetRegisterInfo *TRI = (TargetRegisterInfo
*)MF.getSubtarget().getRegisterInfo();
const TargetMachine &TM = MF.getTarget();
const MCRegisterInfo *MCRI = TM.getMCRegisterInfo();
DEBUG(dbgs() << "Function Name : " <<
2016 May 25
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
Sent from my iPhone
> On May 24, 2016, at 11:04 PM, vivek pandya <vivekvpandya at gmail.com> wrote:
>
>
>
>> On Wed, May 25, 2016 at 10:46 AM, Mehdi Amini <mehdi.amini at apple.com> wrote:
>>
>>> On May 24, 2016, at 10:08 PM, vivek pandya <vivekvpandya at gmail.com> wrote:
>>>
>>>
>>>
>>> On Wed, May 25,
2016 May 11
3
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
Yes there is also MachineRegisterInfo::UsedPhysRegMask which should be the union of all regmasks in the function.
> On May 11, 2016, at 10:47 AM, Hal Finkel via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>
>
>
> From: "Matthias Braun" <matze at braunis.de>
> To: "Hal Finkel" <hfinkel at anl.gov>
> Cc: "vivek pandya"
2016 May 25
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
> On May 24, 2016, at 9:17 PM, vivek pandya <vivekvpandya at gmail.com> wrote:
>
> Dear Mentors,
>
> Please help me to understand our plan to implement Interprocedural Register allocator by propogating register usage info. While writing this mail I am considering all previous discussion over llvm-dev and IRC.
>
> 1) A MachineFunction pass to be executed POST-RA to
2016 May 18
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
*Vivek Pandya*
On Wed, May 18, 2016 at 11:25 PM, Quentin Colombet <qcolombet at apple.com>
wrote:
>
> On May 18, 2016, at 10:46 AM, vivek pandya <vivekvpandya at gmail.com> wrote:
>
>
>
> *Vivek Pandya*
>
>
> On Wed, May 11, 2016 at 4:01 PM, Hal Finkel <hfinkel at anl.gov> wrote:
>
>>
>> ------------------------------
>>
>>
2016 Aug 16
2
A thought to improve IPRA
Hello Mentors,
I did analyze assembly files generated for IPRA + PGO. (1) I observed that
I did not considered the scope of the optimization so changing callee saved
register set for non local function is bad because IPRA can not pass this
information to other modules.
(2) applying this change to indirect function also has no effect because
for such case IPRA is currently not able to propagate
2016 May 25
0
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
----- Original Message -----
> From: "vivek pandya" <vivekvpandya at gmail.com>
> To: "Hal Finkel" <hfinkel at anl.gov>
> Cc: "llvm-dev" <llvm-dev at lists.llvm.org>, "Matthias Braun"
> <matze at braunis.de>, "Mehdi Amini" <mehdi.amini at apple.com>, "Quentin
> Colombet" <qcolombet at
2016 Jul 29
2
A thought to improve IPRA
----- Original Message -----
> From: "vivek pandya" <vivekvpandya at gmail.com>
> To: "Hal Finkel" <hfinkel at anl.gov>
> Cc: "llvm-dev" <llvm-dev at lists.llvm.org>, "Quentin Colombet"
> <qcolombet at apple.com>, "Mehdi Amini" <mehdi.amini at apple.com>
> Sent: Friday, July 29, 2016 5:02:44 AM
>
2016 May 18
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
*Vivek Pandya*
On Wed, May 11, 2016 at 4:01 PM, Hal Finkel <hfinkel at anl.gov> wrote:
>
> ------------------------------
>
> *From: *"vivek pandya" <vivekvpandya at gmail.com>
> *To: *"Mehdi Amini" <mehdi.amini at apple.com>
> *Cc: *"Hal Finkel" <hfinkel at anl.gov>, "Quentin Colombet" <
> qcolombet at
2016 Jul 29
0
A thought to improve IPRA
On Fri, Jul 29, 2016 at 9:01 AM, Hal Finkel <hfinkel at anl.gov> wrote:
> ----- Original Message -----
> > From: "vivek pandya" <vivekvpandya at gmail.com>
> > To: "Mehdi Amini" <mehdi.amini at apple.com>
> > Cc: "llvm-dev" <llvm-dev at lists.llvm.org>, "Hal Finkel" <hfinkel at anl.gov>,
> "Quentin
2017 Mar 14
2
Help understanding and lowering LLVM IDS conditional codes correctly
On 03/14/2017 07:16 AM, vivek pandya wrote:
> Hello Hal,
> setCondCodeAction(expand) for un ordered comparison generates
> semantically wrong code for me for example SETUNE gets converted to
> SETOE that causes infinite loops.
Can you please explain what is happening? It sounds like a bug we should
fix.
>
> What is ideal place where I can convert unordered comparison to un
2016 Aug 05
2
A thought to improve IPRA
The code in X86TargetLowering::IsEligibleForTailCallOptimization() has this part:
// The callee has to preserve all registers the caller needs to preserve.
const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
if (!CCMatch) {
const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
2016 May 25
0
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
----- Original Message -----
> From: "Mehdi Amini" <mehdi.amini at apple.com>
> To: "vivek pandya" <vivekvpandya at gmail.com>
> Cc: "Hal Finkel" <hfinkel at anl.gov>, "llvm-dev"
> <llvm-dev at lists.llvm.org>, "Matthias Braun" <matze at braunis.de>,
> "Quentin Colombet" <qcolombet at
2016 May 11
3
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
*Vivek Pandya*
On Wed, May 11, 2016 at 10:02 AM, vivek pandya <vivekvpandya at gmail.com>
wrote:
>
>
> *Vivek Pandya*
>
>
> On Wed, May 11, 2016 at 9:43 AM, Mehdi Amini <mehdi.amini at apple.com>
> wrote:
>
>>
>> On May 10, 2016, at 6:06 PM, Hal Finkel <hfinkel at anl.gov> wrote:
>>
>>
>>
>>
2016 May 24
0
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
----- Original Message -----
> From: "vivek pandya" <vivekvpandya at gmail.com>
> To: "Quentin Colombet" <qcolombet at apple.com>
> Cc: "Hal Finkel" <hfinkel at anl.gov>, "llvm-dev"
> <llvm-dev at lists.llvm.org>, "Matthias Braun" <matze at braunis.de>,
> "Mehdi Amini" <mehdi.amini at