similar to: Pre/post-increment addressing mode in LSR

Graphcore is a well funded startup that is developing a new processor architecture for accelerating machine-learning applications. We are looking for talented engineers to build world-class development tools that fully exploit the computational capabilities of our architecture. Multiple roles are available - if you enjoy hacking on compilers, debuggers or linkers we would like to speak to you.

Hi Jon, Job postings are ok on the llvm mailing list if and only if they are related to LLVM somehow. Please clarify if this is the case - or if not, please refrain from future posts. Thanks! -Chris > On Apr 12, 2018, at 3:11 AM, Jon Chesterfield via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Graphcore is a well funded startup that is developing a new processor

Hi, I'm looking for some feedback on pain points people have with FileCheck in terms of missing features to help people interested in working on FileCheck to prioritize the work accordingly. I am personally interested in improving FileCheck on 2 issues whenever time permits it: * being able to test for consecutive lines in arbitrary order, i.e. something akin to CHECK-DAG blocks where

Thanks for the suggestions. I think the naming the whole line idea is okay, but it feels a bit clunky. Either we'd have to have a syntax that FileCheck would recognise without caring about the prefix (which seems to be against the ethos of FileCheck, and also makes it less flexible), or in the case I'm referring to, we'd have to have an extra line that does nothing other than define

Any kind of variable definition on a CHECK-NOT line would seem like it would be asking for trouble. Do we allow text variable definitions on a NOT? False fails are better than false matches. Given that it will fail on a line where you'd expect a match, or possibly for the line to be skipped, it's a matter of refining the match expression, which is something that you have to do sometimes

​Hi all, > I feel it might be confusing to have a CHECK becomes effectively a CHECK-NOT, > especially if the RUN line is far from the CHECK line (which is often the case when > a single RUN line drives several groups of CHECK directives (e.g. code generation > tested for several functions for a specific feature, like PIC). You also loose control > on where the NOT should be:

>> Has anyone any idea on how to best handle this? Can LSR "split" an IV >> to use an extra register? Or would this need to be done in a target >> specific pass? > > When you say "an extra address register" would this imply LSR adding > an additional PHI? > > -Hal > Yes, that would have worked well at least in this type of loop. Can LSR

----- Original Message ----- > From: "Jonas Paulsson" <jonas.paulsson at ericsson.com> > To: llvmdev at cs.uiuc.edu > Sent: Monday, November 26, 2012 1:40:24 PM > Subject: [LLVMdev] LSR pass > > > > > > Hi, > > > > I would like some help regarding the LSR pass. It seems that it likes > to duplicate address calculations as in the

Hi, The target supports indexing by register or immediate. Multiplications are not supported by any load / store instructions. Would it be possible to make LSR aware of this? Thanks, Jonas Paulsson -----Original Message----- From: Hal Finkel [mailto:hfinkel at anl.gov] Sent: Saturday, December 01, 2012 5:59 AM To: Jonas Paulsson Cc: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] LSR pass

Hello, For a very simple loop where all IV users are post-inc users, I observed redundant add instructions in AArch64. From LSR debug, I can see initial formula for icmp is the one that transformed to a post-inc form in OptimizeLoopTermCond() and later expanded in post-inc mode. Based on the observation that the icmp is already a post-inc user, I hacked LSR to prevent the icmp from being

> On May 27, 2016, at 2:50 PM, via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hello, > > For a very simple loop where all IV users are post-inc users, I observed redundant add instructions in AArch64. > > From LSR debug, I can see initial formula for icmp is the one that transformed to a post-inc form in OptimizeLoopTermCond() and later expanded in post-inc

Before addressing the CHECK-NOT case, I’m still unclear about the DAG case. What should the first DAG line match? The regex matching would first attempt to match “10 12” but the expression evaluation would fail; so the DAG candidate wouldn’t match; does this mean the DAG matching does not continue searching, and the test fails? Or would we restart the search…. where? With “0 12” (skipping only

Hal, (and everyone who might care about post increment generation)... I have an interesting question/observation. Consider this vector loop. void vec_add_const(unsigned N, short __attribute__ ((aligned (16))) *A, short __attribute__ ((aligned (16))) val) { unsigned i,j; for (i=0; i<N; i++) { for (j=0; j<N; j++) { A[i*N+j] += val; } } } The

Hi all, There have been a few cases recently where I've noticed two test cases in the same lit test that do the same thing except invert the CHECK, to show that something is NOT present. I'm talking about something like the following: # RUN: llvm-sometool --print-string | FileCheck %s --check-prefix=STRING # RUN: llvm-sometool --no-print-string | FileCheck %s --check-prefix=NO-STRING #

I ran into an LLVM/Clang crash when attempting to do the following: 1. Build Clang from the release/9.x branch source. 2. Use the Clang from (1) to build clangd on the release/9.x branch, with LLVM_ENABLE_MODULES=On. I wrote a script to reproduce the crash: https://gist.github.com/modocache/ac366ca9673b93bb21e75d3e72162608 At the above URL, you'll find a script `repro.sh` that reproduces

Hi, We wrote an optimization that eliminates common sub-expressions in a group of similar GEPs for the NVPTX backend. It speeds up some of our benchmarks by up to 20%, which convinces us to try to upstream it. Here's a brief description of why we wrote this optimization, what we did, and how we did it. Loops in CUDA programs are often extensively unrolled by programmers and compilers,

Hi All, I have a question regarding LLVM backend. I appreciate a lot if anyone can provide some hints. My work here is to avoid base+index address mode for X86 target, to allow base-register only or index-register only address mode. For example, "mov (%rsi), %rbx" is allowed, but "mov (%rsi, %rax), %rbx" is not allowed. I understand LLVM backend is a complex system. Can any

I'm happy to announce that Apple is contributing some major extensions to the LLVM ARM backend. The improvements include support for ARM v4/v6, vfp support, soft float, pre/postinc support, load/ store multiple generation, constant pool entry motion (to support large functions), and support for the darwin/arm ABI. In addition to ARM support, the backend now includes code generation

Hello- I have a low traffic AAH setup, a few hardphones, a few softphones, 50 calls per day max. I used the AMP Digital Receptionist to make a simple voice menu: "Thank you for calling xxxx". I did this for both Normal times and After Hours times. It worked fine. I then went to the AMP Maintenance window, Config Edit, got the "phpconfig for Asterisk PBX" page, and selected

----- Original Message ----- > From: "Sergei Larin" <slarin at codeaurora.org> > To: "Hal Finkel" <hfinkel at anl.gov> > Cc: llvmdev at cs.uiuc.edu > Sent: Friday, March 1, 2013 10:24:39 AM > Subject: Interesting post increment situation in DAG combiner > > Hal, (and everyone who might care about post increment generation)... Sergei, Perhaps