Displaying 20 results from an estimated 3000 matches similar to: "[GlobalISel] Quick Status"
2020 May 12
3
Codegen pass configs dependent on function attributes?
I’ve put up a patch here: https://reviews.llvm.org/D79769 <https://reviews.llvm.org/D79769> that adds a unified pipeline that targets can opt-into. It has some similarities with forcing fallbacks, but uses a different mechanism to do so to preserve the abort behavior. It therefore requires that every GISel pass needs to explicitly check whether the GISel selector is being requested rather
2020 May 05
4
Codegen pass configs dependent on function attributes?
Hi all.
I’m trying to get GlobalISel to work better with LTO. At the moment if you enable it via -fglobal-isel, it only adds the -mllvm -global-isel and related options to the cc1 invocation. With LTO, that doesn’t work as we need to encode codegen options into the bitcode, usually via function attributes.
Does anyone have any ideas on how to achieve this? The only way I can see it working is if
2017 Jun 16
7
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
Hi all,
We had some internal discussions about flipping the default for O0 and we concluded that we wanted to postpone it.
*** Why Is That? ***
We don’t want to send the wrong message that GlobalISel’s design is set in stone and ready for broader adoption.
In particular,
1. The APIs are still evolving and can still possibly change significantly
2. The TableGen backend to reuse the existing SD
2017 Jul 06
2
[RFC][GlobalISel] Making GlobalISel non-optional in the build
Hi,
I would like to get rid of the logic around disabling GlobalISel from the build.
*** Context ***
So far, GlobalISel has been this framework built up on the side for about two years. Now, we are close to a point where having it being optional impedes our ability to implement the right things. For instance, checks that would fit naturally in the MachineVerifier are directly done during the
2017 Nov 13
3
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
Hi Quentin,
My only remaining concern is around ABI compatibility.
The following commit seems to indicate that in the previous round of evaluation, we didn’t find an existing ABI compatibility issue:
http://llvm.org/viewvc/llvm-project?view=revision&revision=311388.
I haven’t looked into the details of this issue - so maybe I’m worried over nothing?
I’m wondering if since then on your side
2017 Apr 27
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
Hi Kristof,
> On Apr 27, 2017, at 9:47 AM, Kristof Beyls <kristof.beyls at arm.com> wrote:
>
> Hi Quentin,
>
>> On 27 Apr 2017, at 00:48, Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote:
>>
>> Hi Kristof,
>>
>>> On Apr 6, 2017, at 6:53 AM, Kristof Beyls <kristof.beyls at arm.com
2017 Jan 17
2
RFC: Building GlobalISel by default
Hi Michael,
> On Jan 13, 2017, at 6:38 PM, Michael Kuperstein <mkuper at google.com> wrote:
>
> As a person not developing on GlobalISel, I can already play with it by setting the flag. ;-)
>
> The main (and huge) benefit I see is that it will get tested by default.
I agree.
> So, I think it's mainly a question of maturity - if my (non-GlobalISel) change breaks
2017 May 09
4
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
Great Quentin :).
I've rerun the benchmarks comparing "-O0 -g" with "-O0 -g -mllvm -global-isel -mllvm -global-isel-abort=2" on r302453, on AArch64 Cortex-A57.
I indeed see almost no moves between GPR and FPR registers anymore (see details below for where I still see some).
On geomean, I see 13% slow down (down from 17% on my previous run).
On geomean, code size increase
2017 Apr 26
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
Hi Kristof,
> On Apr 6, 2017, at 6:53 AM, Kristof Beyls <kristof.beyls at arm.com> wrote:
>
> I've been digging a little bit deeper into the biggest performance regressions I've observed.
>
> What I've observed so far is:
> * A lot of the biggest regressions are caused by unnecessarily moving floating point values through general purpose registers. I've
2020 Feb 27
2
Correct modelling of instructions with types smaller than the register class
Hi Quentin, Hi Amara,
I was following your discussion on D75086 regarding declaring types as
legal even if they are smaller than the actual register class (e.g. s16
and gpr32). We are working on a backend which only has 32 and 64-bit
registers and we recently had a problem regarding exactly this where we
had to declare G_UNMERGE_VALUES and G_MERGE_VALUES with a smaller type
of <s32 as
2017 Nov 14
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
Hi Quentin,
I’ve started running an ABI test suite with global isel on AArch64, and while it hasn’t found any ABI issues it has hit an assertion in clang when using the __fp16 type. Here’s a reproducer:
__fp16 pass_f16(__fp16 p) {
return p;
}
$ /work/llvm/build/bin/clang --target=aarch64-arm-none-eabi -march=armv8-a -c test.c -O0 -mllvm -global-isel -mllvm -global-isel-abort=0
2017 May 09
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
Hi Quentin,
On Tue, May 9, 2017 at 11:47 AM Quentin Colombet via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> Hi Kristof,
>
> On May 9, 2017, at 3:41 AM, Kristof Beyls <kristof.beyls at arm.com> wrote:
>
> Great Quentin :).
>
> I've rerun the benchmarks comparing "-O0 -g" with "-O0 -g -mllvm
> -global-isel -mllvm
2017 Nov 14
6
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
To give an update here, we actually are not missing a mapping. The code complains because we are copying around a fp16 into a gpr32 and that shouldn’t be done with a copy (default mapping).
I extended the repairing code to issue G_ANYEXT in those cases instead of asserting.
However, now, I have to teach instruction select about those ANYEXT otherwise we’ll fallback in that case. But that’s a
2017 Nov 17
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
Hi Oliver,
Thanks for trying this.
Could you file a different PR for each of the problem you found and reference the umbrella PR: http://llvm.org/PR35347? <http://llvm.org/PR35347?>
Thanks,
-Quentin
> On Nov 17, 2017, at 8:17 AM, Oliver Stannard <oliver.stannard at arm.com> wrote:
>
> Hi Quentin,
>
> One more reproducer, this time with small (<64bit) values
2020 Mar 02
2
Correct modelling of instructions with types smaller than the register class
Hi Quentin,
thank you for the reply! This clears up a lot of the questions I was
having. It seems like we should definitely invest some time in rewriting
some of our legalization rules then! I also posted some questions
further down below. I would appreciate getting your opinion on them.
> Hi Dominik,
>
> I’ll do a brief reply here and if you want more information we can talk further
2019 Jun 20
2
RFC: Memcpy inlining in IR
Looks like there are a lot of opinions where memcpy expansion/inlining needs to happen: (late) IR, or if it is a backend problem, see also for example https://reviews.llvm.org/D35035. Complicating factor here is that efficient memcpy lowering is crucial for performance and code-size (and they occur a lot).
Either way, I agree that the TLI hooks are not SelectionDAG specific, they can be used in
2017 Nov 27
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
Thanks all.
Amara, could you take a look?
> On Nov 20, 2017, at 3:06 AM, Oliver Stannard <oliver.stannard at arm.com> wrote:
>
> Hi Quentin,
>
> I’ve raised:
> https://bugs.llvm.org/show_bug.cgi?id=35359 <https://bugs.llvm.org/show_bug.cgi?id=35359>
> https://bugs.llvm.org/show_bug.cgi?id=35360 <https://bugs.llvm.org/show_bug.cgi?id=35360>
>
2017 Mar 29
4
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
Hi,
GlobalISel, the SelectionDAG replacement, has come a long way since initially discussed on the mailing list and its last discussion at the EuroLLVM BoF (https://etherpad.net/p/GlobalISel <https://etherpad.net/p/GlobalISel>).
We believe we are close to the point of enabling it by default on AArch64 at O0. We now would like to enlist your help to get there.
*** Quick Status ***
On iOS
2017 Apr 03
5
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
I've kicked off a run to compare "-O0 -g" versus "-O0 -g -mllvm -global-isel -mllvm -global-isel-abort=2".
I've selected the test-suite (albeit a version which is a couple of months old now) and a few short-running proprietary benchmarks to get data back quickly for an initial feel of where things are.
This was running on Cortex-A57 AArch64 Linux.
I saw one assertion
2017 Jan 14
13
RFC: Building GlobalISel by default
Hi all,
Now, four backends (if I am counting right: X86, ARM, AArch64, AMDGPU) are working on bringing-up GlobalISel, I’d like to switch the default of the LLVM_BUILD_GLOBAL_ISEL variable in CMake, such that the framework gets built by default.
** Impact of Flipping the Switch **
* Upsides *
For people developing on GlobalISel, it will:
- Simplify the CMake command to type :)
- Build/Test