similar to: [PATCHish] IfConversion; lost edges for some diamonds

On Tue, Oct 10, 2017 at 4:48 PM, Friedman, Eli via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 10/9/2017 3:10 AM, Gaël Jobin via llvm-dev wrote: > > Hi all, > > I got a silly bug when compiling our project with the latest Clang. Here's > the outputted assembly: > > tst r3, #255 > strbeq r6, [r7] > ldreq r6, [r4, r6, lsl #2] > strne r6, [r7, #4]

On Wed, Oct 31, 2012 at 09:13:43PM +0100, Bjorn De Sutter wrote: > Hi all, > > I am working on a CGRA backend (something like a 2D VLIW), and we also absolutely need predication. I extended the IfConversion pass to allow it to be executed multiple times and to predicate already predicated code. This is necessary to predicate code with nested conditional statements. At this point, we

Hi all, I am working on a CGRA backend (something like a 2D VLIW), and we also absolutely need predication. I extended the IfConversion pass to allow it to be executed multiple times and to predicate already predicated code. This is necessary to predicate code with nested conditional statements. At this point, we support or, and, and conditional predicates (see Scott Mahlke's papers on this

Evan, et al., I've come across a small issue when using the if conversion pass in PPC to generate conditional returns. Here's a small example: ** Before if conversion ** BB#0: derived from LLVM BB %entry %R3<def> = LI 0 %CR0<def> = CMPLWI %R3, 0 BCC 68, %CR0, <BB#3> Successors according to CFG: BB#3(16) BB#1(16) BB#1: derived from LLVM BB

In the section expaining "dyn_cast" There are following lines of code: if (AllocationInst *AI = dyn_cast<AllocationInst>(Val)) { ... } I cannot understand how you take a operand, a value, and cast it into a Instruction. Can you explain it for me? Another common example is: // Loop over all of the phi nodes in a basic block BasicBlock::iterator BBI =

Hi all! I have a problem setting ACLs on a remote file on a Windows XP Pro SP2 box. I issue the following command: smbcacls -a 'ACL:BBI-DEV\beakid:ALLOWED/0/0x00100116' -U 'BBI-DEV \Admin' //BBI-DEV/Data /Niva.txt And I get this response from debug level 3. Password: Connecting to host=BBI-DEV Connecting to 192.168.1.124 at port 445 Doing spnego session setup (blob

Hi all! I have a problem setting ACLs on a remote file on a Windows XP Pro SP2 box. I issue the following command: smbcacls -a 'ACL:BBI-DEV\beakid:ALLOWED/0/0x00100116' -U 'BBI-DEV \Admin' //BBI-DEV/Data /Niva.txt And I get this response from debug level 3. Password: Connecting to host=BBI-DEV Connecting to 192.168.1.124 at port 445 Doing spnego session setup (blob

Thanks for the review Gordon. On Tue, Nov 1, 2011 at 2:21 AM, Gordon Henriksen <gordonhenriksen at mac.com>wrote: > On 2011-10-31, at 17:21, Nicolas Geoffray wrote: > > > Here's a patch to allow a GCStrategy to customize the places where it > wants to insert safe points. I'm not sure who maintains the GC code today > in LLVM (I'd be happy to take ownership, if

On Nov 1, 2011, at 4:47 AM, Nicolas Geoffray <nicolas.geoffray at gmail.com> wrote: > Thanks for the review Gordon. > > On Tue, Nov 1, 2011 at 2:21 AM, Gordon Henriksen <gordonhenriksen at mac.com> wrote: > On 2011-10-31, at 17:21, Nicolas Geoffray wrote: > > > Here's a patch to allow a GCStrategy to customize the places where it wants to insert safe points.

On 4/10/2013 12:45 PM, Hal Finkel wrote: > > Should AnalyzeBranch be enhanced to somehow indicate conditional returns? I don't think that returns can ever be analyzable (since LLVM's CFG does not have a designated exit block). > Alternatively, the diamond conversion routine contains this: > > // RemoveExtraEdges won't work if the block has an unanalyzable branch,

my compiler gave me a warning in MCObjectDisassembler.cpp. it found a self-comparation in loop condition. I think it's a typo. the suspicious code was introduced by this patch: >From f176482752fbea3139394e280adfb10270dd3aac Mon Sep 17 00:00:00 2001 From: Ahmed Bougacha <ahmed.bougacha at gmail.com> Date: Wed, 21 Aug 2013 07:28:55 +0000 Subject: MC CFG: Support disassembly at

Any chance of adding some missing test coverage here? That code was dead (& evidently untested) before... On Thu, Jul 31, 2014 at 11:37 AM, Eric Christopher <echristo at gmail.com> wrote: > I believe you are correct. Fixed thusly: > > dzur:~/sources/llvm> git svn dcommit > Committing to https://llvm.org/svn/llvm-project/llvm/trunk ... > M

Hi, TL;DR: A loop doesn't get vectorized due to the interaction of loop- rotate, licm and instcombine. What to do about it? Full story: In the benchmarks for our out-of-tree target we have a case that we would like to get vectorized, but currently it isn't. I've done some digging to see why and have some kind of idea what prevents it, but I don't know what the best way to fix

Hello, I have a few questions about applying the IfConversion pass to my out-of-tree target. (1) Is it true that the IfConversion pass may only run after register allocation? I often encounter this bad scenario, and I think it could be entirely avoided if IfConversion ran before register allocation: the block-to-be-predicated contains load-immediate (LI) instructions. The LI instructions

Hi All, How can I run the IfConversion pass in JIT to optimize my code for ARM as a Target Architecture? -- View this message in context: http://llvm.1065342.n5.nabble.com/Machine-level-IfConversion-for-ARM-tp69513.html Sent from the LLVM - Dev mailing list archive at Nabble.com.

Assume an architecture that has multiple condition code registers, e.g., powerpc. Now assume that there are predicate instructions like thumb2, but can specify which condition code register they refer to. Now also assume that these predicate instructions themselves are predicatible, if executed they change the current predication state. Can LLVM handle multiple levels of predication? When is

Hi all, I am using llvm backend to generate binary for a specific accelerator. I would like to convert instructions into predicated form when instructions are still in SSA form. It looks like that ifconversion execution flow is different when instructions are in SSA form. However, I am encountering many problems (specially with registers) when I use it before register allocation. I was wondering

Hello! The if-converter tries to match 'Simple' patterns looking like this: // Simple (split, no rejoin): // EBB // | \_ // | | // | TBB---> exit // | // FBB The IfConverter::ValidSimple method (lib/CodeGen/IfConversion.cpp:461) checks if TBB matches this pattern. It basically does this by simply checking if AnalyseBranch fails on

Hi. On our system we have a problems with recursive IfConversion algorithm. Here is the patch for making it loop-based. Or do I need to send it to some other mail-list? -- Best regards, Andrew Zhogin. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130701/f526e1f0/attachment.html> -------------- next

Hi, I am trying to implement support for an if-conversion pass in a backend for the ADRES CGRA architecture. >From studying the existing IfConversion pass, I observed the following: - The PredicateInstruction method is meant to insert guards into conditional instructions. - This method assumes that one will be able to get the predicate from the conditional branch instruction on which