similar to: Conditional jump or move depends on uninitialised value(s)

Displaying 20 results from an estimated 400 matches similar to: "Conditional jump or move depends on uninitialised value(s)"

2016 Nov 22
2
Conditional jump or move depends on uninitialised value(s)
Just want to emphasize that on x86-64 and using Valgrind: LLVM compiled with LLVM gets 360 unexpected test fails LLVM compiled with GCC gets 22 unexpected test fails Of course I don't know how many of these are caused by this bitfield speculation issue. John On 11/21/2016 10:48 PM, regehr via llvm-dev wrote: > Alright, here's what seems to be happening... > > The testcase
2010 Apr 14
2
[LLVMdev] Default behavior of DeadMachineInstructionElim deletes all instructions
I've recently sync'd to a newer version of LLVM(Apple branch 2326 from Apple branch 2323.8) that changed the interface to addCommonCodeGenPasses which caused the default implementation to be executed instead of my overriding implementation. This default implementation has DeadMachineInstructionElim pass enabled, which is causing havoc with my backend. Before entering this pass, everything
2010 Apr 14
2
[LLVMdev] Default behavior of DeadMachineInstructionElim deletes all instructions
Dale, Yeah that is correct, so that isn't the problem, not sure why I was thinking it is. The !MRI->use_no_dbg_empty(Reg) seems to be correct and the problem is LivePhysRegs[Reg] always returning false. I've looked into this more and there is a part where I'm working with physical registers. If there is a function call, there is a copy from virtual register space to the functions
2010 Apr 14
0
[LLVMdev] Default behavior of DeadMachineInstructionElim deletes all instructions
On Apr 14, 2010, at 1:55 PMPDT, Villmow, Micah wrote: > I’ve recently sync’d to a newer version of LLVM(Apple branch 2326 from Apple branch 2323.8) that changed the interface to addCommonCodeGenPasses which caused the default implementation to be executed instead of my overriding implementation. This default implementation has DeadMachineInstructionElim pass enabled, which is causing havoc
2016 May 11
2
[LLVMdev] Improving the quality of debug locations / DbgValueHistoryCalculator
> On May 11, 2016, at 1:12 PM, Francois Pichet <pichet2000 at gmail.com> wrote: > > Hello, > > Regarding the problem of debug range for optimized code. > Currently a DEBUG_VALUE will be inserted after the <def>vregX > DEBUG_VALUE are only valid until the end of the current MachineBasicBlock. That's the main problem. > Why not simply iterate over all uses
2016 May 11
2
[LLVMdev] Improving the quality of debug locations / DbgValueHistoryCalculator
> On May 11, 2016, at 2:09 PM, Francois Pichet <pichet2000 at gmail.com> wrote: > > Good point. > > Currently yes a DEBUG_VALUE "x", vreg0 will be added in BB2. Now I realize this might be wrong in some (corner?) cases where vreg0 no longer refer to "x" > > My fix would be to propagate the DEBUG_VALUE only if "x" is associated with only a
2016 May 11
3
[LLVMdev] Improving the quality of debug locations / DbgValueHistoryCalculator
The most obvious place where it is lacking at the moment is that it only supports DBG_VALUEs in registers. Adding support for constant values, memory locations, and fp constants would be a big win! thanks, Adrian > On May 11, 2016, at 2:52 PM, Francois Pichet <pichet2000 at gmail.com> wrote: > > In retrospect I totally agree with you. I am looking at LiveDebugValue again to see
2016 May 12
2
[LLVMdev] Improving the quality of debug locations / DbgValueHistoryCalculator
> On May 12, 2016, at 11:00 AM, Francois Pichet <pichet2000 at gmail.com> wrote: > > Here is a specific case that make the debugging experiences degraded on my target: > This is a loop simplified CFG: > > BB#0: > %R5<def> = OR_rr %R0, %R49 // this is %R5 only def. > DBG_VALUE %R5, %noreg, !"argc", <!18>; line no:4 > Successors
2012 Nov 29
2
[LLVMdev] operator overloading fails while debugging with gdb for i386
For the given test: class A1 { int x; int y; public: A1(int a, int b) { x=a; y=b; } A1 operator+(const A1&); }; A1 A1::operator+(const A1& second) { A1 sum(0,0); sum.x = x + second.x; sum.y = y + second.y; return (sum); } int main (void) { A1 one(2,3); A1 two(4,5); return 0; } when the exectable of this code is debugged in gdb for i386, we dont get the
2018 Feb 09
0
retpoline mitigation and 6.0
On Fri, 2018-02-09 at 12:54 +0000, David Woodhouse wrote: > On Fri, 2018-02-09 at 10:36 +0000, David Woodhouse wrote: > >  > > Did you get anywhere with the function attribute? Having isolated the > > next boot failure to "it goes away if I compile io_apic.c without > > retpoline", bisecting it per-function would help to further delay the > > bit where I
2011 Jun 02
0
[LLVMdev] Advice on MachineMoves and SEH
On Jun 2, 2011, at 6:20 AM, Rafael Ávila de Espíndola wrote: > On 11-06-02 6:56 AM, Anton Korobeynikov wrote: >> Hi Chip, >> >>> Because of all this, it's hard to reconstruct the SEH information from >>> the MachineMove array. I have thought about adding a new array specific >>> to SEH information, but I'm not sure how you guys would feel about
2012 Dec 01
0
[LLVMdev] operator overloading fails while debugging with gdb for i386
Problem seems not only with operator overloading, It occurs with struct value returning also. gdb while debugging expects the return value in eax, gcc does returns in eax, But Clang returns in edx(it can be checked in gdb by printing the contents of edx). Code(sample code) struct A1 { int x; int y; }; A1 sum(const A1 one, const A1 two) { A1 plus = {0,0}; plus.x = one.x + two.x; plus.y
2012 Dec 01
2
[LLVMdev] operator overloading fails while debugging with gdb for i386
Hi, Structures are passed by pointer, so the return value is not actually in eax. That code gets transformed into something like: void sum(A1 *out, const A1 one, const A1 two) { out->x = one.x + two.x out->y = one.y + two.y } So actually the function ends up returning void and operating on a hidden parameter, so %eax is dead at the end of the function and should not be being relied
2010 Apr 29
0
[LLVMdev] Default behavior of DeadMachineInstructionElim deletes all instructions
Ping. Anyone have any idea on how to fix this? Thanks, Micah From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Villmow, Micah Sent: Wednesday, April 14, 2010 2:28 PM To: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] Default behavior of DeadMachineInstructionElim deletes all instructions Dale, Yeah that is correct, so that isn't the problem, not sure
2017 Aug 03
2
Re-computing Live-in/Live-out Physical Registers for Basic Blocks Using LivePhysRegs
Thank you for your reply! If liveness of APSR is not tracked, how does the code generator determine whether instructions like cmp are dead code or not? Is it true that, for every use of APSR (such as a conditional branch), the used def (such as cmp, add, etc.) is always in the same basic block? Is it true that APSR is never assumed to live across basic block boundaries? Thank you! Ming Zhang
2015 Aug 12
3
[LLVMdev] Improving the quality of debug locations / DbgValueHistoryCalculator
Hi all, An early implementation of extending debug ranges and providing multiple location support is done here: http://reviews.llvm.org/D11933 Design document: https://docs.google.com/document/d/1noDVWTvTWBdYdweICPBwvwyt8QvX4KHl7j3XKNSg1nE/edit?usp=sharing On Jun 24, 2015, at 12:12 PM, Alexey Samsonov <vonosmas at gmail.com> wrote: Hi Adrian, You might want to take a look at abandoned
2014 Oct 14
2
[LLVMdev] Thoughts on maintaining liveness information for stackmaps
Hi all, I've run into a couple bugs recently that affected stackmap liveness analysis in various ways: http://llvm.org/bugs/show_bug.cgi?id=19224 - function arguments stay live unnecessarily http://llvm.org/bugs/show_bug.cgi?id=21265 - eflags can end up as a live out http://llvm.org/bugs/show_bug.cgi?id=21266 - %rip can end up as a live out The first two have nothing to do with stackmaps
2010 May 03
2
[LLVMdev] Default behavior of DeadMachineInstructionElim deletes all instructions
On Apr 29, 2010, at 2:06 PM, Villmow, Micah wrote: > Ping. Anyone have any idea on how to fix this? Does your getAllocatableSet() return a BitVector that is at least getNumRegs() bits long? Otherwise this doesn't work: BitVector NonAllocatableRegs = TRI->getAllocatableSet(MF); NonAllocatableRegs.flip();
2014 Oct 14
2
[LLVMdev] Thoughts on maintaining liveness information for stackmaps
I think what's happening is BranchFolder::MaintainLiveIns is using a forward analysis on top of these missing kill flags, and updating the BB-live-ins/live-outs with an incorrect set of registers. Then when the stackmaps liveness analysis happens, it's not doing anything wrong, but it starts with the wrong set of live registers and will propagate those to the point of the
2018 Feb 09
2
retpoline mitigation and 6.0
On Fri, 2018-02-09 at 10:36 +0000, David Woodhouse wrote: > > Did you get anywhere with the function attribute? Having isolated the > next boot failure to "it goes away if I compile io_apic.c without > retpoline", bisecting it per-function would help to further delay the > bit where I actually have to start *thinking*... It's mp_register_ioapic(), and only when