similar to: how to prevent LLVM back-end from reordering instructions at instruction scheduling?

I have the same issue, would it be easier and more useful to attach a flag to the instruction to tell the scheduler not to move instructions across this boundary? -Ryan On Tue, Nov 15, 2016 at 5:11 PM, Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > You can create a DAG mutation that adds artificial dependencies between A, > B and Z. > > -Krzysztof >

Setting the MI as isTerminator should have the same impact, yes? I'm not sure of the other consequences of this though, if any, have to look into it. Thanks. -Ryan On Tue, Nov 15, 2016 at 5:18 PM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > You can override TargetInstrInfo::isSchedulingBoundary for that. > > -Krzysztof > > On 11/15/2016 4:13 PM, Ryan