similar to: Runtime error

Hi Developer, In my processor I am not using registers so I wrote Simple register.td file with bare minimum functions. But when I am registering my target with llvm it is showing "*Segmentation Fault(core dumped)*" Error and also same error while generating table-gen for asm-writer. Some one told comment out EditRegesterName function. because this error is due to EditRegisterName it

Hi Developers, I have written C program and want to generate IR file for Specific Target I have tried with following command but got a error as follows, COMMAND: *clang -S -emit-llvm -march=leg ~/llc-test-examples/ex9.c -o ~/llc-test-examples/ex9.ll* ERROR: *error: unknown target CPU 'leg'* So any please help me what all other step should I do previously to get my *leg* target in clang.

HI developers, I want to add trigonometric instructions in my instrinfo.td files how can i directly map these instructions in .td files. Please help me Guys.For Sin, Cos, Tan and Cot Instructions. If I used llvm.sin.* as SDNode Then it is error as llvm variable is not defined SO please Help me. Thanks and Regards Varun -------------- next part -------------- An HTML attachment was scrubbed...

I want to insert new alloca Instruction after existing alloca Instruction in llvm pass so what attribute to be passed at last in following newallocaI = new AllocaInst(llvm::Type::getInt32PtrTy(context,0), //type 0, // ArraySize 8, // Alignment

Hi Developer, While generating CodeEmitter.inc I got following error which i am attaching as screen short as follows Please help me guys. If you want other info I will provide you guys Thanks and Regards Varun -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20161028/29ec72e6/attachment-0001.html>

I am new to writing LLVM pass so please help me. I want to replace my pure load instruction like %a = alloca i32, align 4 %0 = load i32, i32* %a, align 4 to the load from getElementPtr like %a = alloca i32, align 4 %p = alloca i32*, align 8 store i32* %a, i32** %p, align 8 %0 = load i32*, i32** %p, align 8 %1 = load i32, i32* %0, align 4 How to write LLVM pass to replace the above? Thanks

I have a simple program that generates correct intermediate representation. However, when working on my backend, and my lowering function gets called. The comparison operation is flipped via an invalid transformation. i.e. gt ==> le, lt ==> ge etc.. define void @test_fc_if_gt(double %x, double %y, double addrspace(11)* %result) { entry: %x.addr = alloca double ;

On Mon, Nov 10, 2008 at 3:06 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > With the above kernel run through llc with -march=x86 > -view-dag-combine1-dags I still see the ogt as the comparison operation, but > when I run it with llc -march=x86 -view-legalize-dags the ogt node has been > transformed into a ule. Okay... I can see that in the attached graph. > So, my

Hello all, I am currently working with LLVM and make use of the debug output from llc. The SelectionDAG dumping features are especially interesting to me since I am looking for operation patterns that allow me to decide which custom instructions can be added to a processor in order to improve the performance. Providing a -view-dag-combine1-dags option (and its friends) to llc show the

Hi Varun, I see the point of your question, but I'm not the best person to answer from that perspective. Nadav Rotem is the owner of the x86 backend, and he can probably give you a more complete answer than I could. Thanks, Andy From: Varun Agrawal [mailto:vagrawal at cs.stonybrook.edu] Sent: Friday, October 11, 2013 8:48 PM To: Kaylor, Andrew; llvmdev at cs.uiuc.edu Subject: RE: Building

Hi Andrew, I think I diluted my question. My question was not related to MCJIT. I ran the following 4 scenarios: (1)gcc -mcpu=corei7 tetris.c -o tetris (2)gcc -mcpu=athlon64 tetris.c -o tetris (3)clang -march=corei7 tetris.c -o tetris (4)clang -march=athlon64 tetris.c -o tetris In (1) and (2), I see difference in order of instructions in the output binaries, which I expected because every CPU

By default the prototype.js gives us the function /* prevent memory leaks in IE */ Event.observe(window, ''unload'', Event.unloadCache, false); But there is no unload event in out application as the content of the div keeps changing using the Ajax.Updater function. To handle such a scenario, we''ve added the following lines of code to prototype.js /* prevent

On Wed, Sep 10, 2008 at 2:35 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > Generating the following LLVM IR: > > define void @test_unary_op_anegate(float %x, float addrspace(11)* %result) > nounwind { > entry: > %neg = sub float -0.000000e+000, %x ; <float> [#uses=1] > store float %neg, float addrspace(11)* %result >

Hi, 1. I have 2 panes, each having approximately 45-50 slides, all the slide images are 110x82 pixels in size, enclosed in their respective div''s. 2. These divs are further enclosed in a parent div, which is defined as a Sortable on page load. 3. There is a destination div on the RHS also. Sortable.create("div_leftDiv", {ghosting:true, revert: true, dropOnEmpty:true,

Hi Varun, Have you tried your experiment with icc by any chance? The MCJIT component does not assume that you will be executing the generated code on the host system because it can be used to generate code for external targets. However, you can specify the CPU by calling setCPU() on the EngineBuilder object before creating your execution engine. (You can use sys::getHostCPUName() to figure out

In Sortables, we have a function onHover: onHover: function(element, dropon, overlap) { if(overlap>0.5) { Sortable.mark(dropon, ''before''); if(dropon.previousSibling != element) { var oldParentNode = element.parentNode; element.style.visibility = "hidden"; // fix gecko rendering

Hi, I am experimenting with libnetfilter_queue. libnetfilter_queue is a userspace library providing an API to packets that have been queued by the kernel packet filter. I am using sample code(nfqnl_test.c) available on netfilter.org. I have generated two binaries (queue0 and queue1) using that nfqnl_test.c sample code. These binaries are working as per expected behaviour in case of Centos 6.2

Hi, I was trying to attach console to my virtual node created by xen but I am getting the following error: *varun:~# xm console xenDomain1* *xenconsole: Could not read tty from store: No such file or directory.* I have tried starting the xenconsoled service but still I am facing the same problem. Can anyone please help me out with this one? Regards, Varun

Hi Nicolai, I think there are two distinct, somewhat loosely connected questions here: 1. Spelling out the (existing, implicit) policy explicitly in the documentation. 2. What the actual policy is and potentially changing it to make things easier for downstream. I started this thread with the intention of tackling 1 and not 2. I think the conversation around 2 is much harder as it will require

On Sep 16, 2009, at 5:58 AM, Kenneth Uildriks wrote: >> I recently made a major reorganization of the calling-convention >> lowering code which cleared away one of the major obstacles to >> doing this within codegen. >> >> Dan > > So what was the obstacle, and how was it cleared? The biggest obstacle is that there used to be two different methods for lowering