similar to: Creating a clang-tidy const position check

Hi, For the development of a new micro-controller backend, I try to lowering the following store SDNode: t5: ch = store<ST2[%ptr2](align=4)> t0, Constant:i16<3>, FrameIndex:i16<1>, undef:i16 I have defined the following instruction and associated DAG pattern. def MOVSUTO_A_i32o : CLPFPU_A_i32o_Inst<0b1000001101,

Hi, I am looking at the Type Based Alias Analysis and I am trying to understand why, from what I see, pointsToConstantMemory() never returns true. It seems that this information should come from the TBAA metadata, in which the Access Tag has an optional 4th field to specify this information. "Access tags are represented as MDNode s with either 3 or 4 operands. The first operand is an

Hi, all, I am planning to add clang-tidy checkers for my company. How to add a new module for my company? Please help, thanks in advance. I try to copy files from cert module, and rename cert to Misra, then add a rule named "m-0-1-1" by ./add_new_checker.py. then I run ninja check-clang-tool, but my case is failed due to below error Running ['clang-tidy',

You need to specify sub-register == super-register, idx relationship. See X86RegisterInfo.td: def x86_subreg_8bit : PatLeaf<(i32 1)>; def x86_subreg_16bit : PatLeaf<(i32 2)>; def x86_subreg_32bit : PatLeaf<(i32 3)>; def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI, R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W], [AL, CL,

On Thu, 2008-10-02 at 11:19 -0700, Evan Cheng wrote: > > On Oct 2, 2008, at 11:02 AM, Sanjiv.Gupta at microchip.com wrote: > > > What’s the value produced by an INSERT_SUBREG node? Is it a chain? > > > No, insert_subreg returns a value: > > > v1 = insert_subreg v2, v3, idx > > > v1 and v2 will have the same type, e.g. i16, and v3 must have a >

I was looking at the ClassTemplatePartialSpecializationDecl::getInstantiatedFromMember documentation, in the included example it says: "(..) the instantiation of Outer<float>::Inner<int*> will end up instantiating the partial specialization Outer<float>::Inner<U*> (...)". To understand the concept better, I dumped the AST for the following code:

On Tue, 2008-10-14 at 10:19 -0700, Evan Cheng wrote: > You need to specify sub-register == super-register, idx relationship. > See X86RegisterInfo.td: > > def x86_subreg_8bit : PatLeaf<(i32 1)>; > def x86_subreg_16bit : PatLeaf<(i32 2)>; > def x86_subreg_32bit : PatLeaf<(i32 3)>; > > def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI, >

Hi, I'm implementing __builtin_setjmp and __builtin_longjmp for Sparc 32 bit processors (64 bit later, time allowing). I'm basing the code on the PowerPC version, which itself is based on the X86 version. This code is very nearly working, and I've had it working for -O0 optimisation (with a slightly different version to that below), so I know it's close. However, the PowerPC

On Tue, Mar 29, 2016 at 11:20 PM Robinson, Paul < Paul_Robinson at playstation.sony.com> wrote: > Skipping a serialization and doing something clever about LTO uniquing > sounds awesome. I'm guessing you achieve this by extracting types out of > DI metadata and packaging them as lumps-o-DWARF that the back-end can then > paste together? Reading between the lines a bit

On Tue, Mar 29, 2016 at 11:50 PM, Eric Christopher via cfe-dev < cfe-dev at lists.llvm.org> wrote: > > > On Tue, Mar 29, 2016 at 11:20 PM Robinson, Paul < > Paul_Robinson at playstation.sony.com> wrote: > >> Skipping a serialization and doing something clever about LTO uniquing >> sounds awesome. I'm guessing you achieve this by extracting types out of