similar to: scheduler options documentation?

I think those should be considered internal options for (llvm codegen) developers, a normal compiler user should not need to use any of them. Of course you can look around the llvm sourcecode (esp. in lib/CodeGen/MachineScheduler.cpp) and see what cl::opt options are available and how they affect the scheduler operation. In case of the MachineScheduler all settings are the same regardless of the

In order for our instruction itineraries to be considered by the instruction scheduler we seem to have to pass -enable-misched to llvm: clang -O3 -mllvm -enable-misched -c some.c ..... If -enable-misched isn't included there it doesn't seem to take our instruction itineraries into account. What's the best way to make '-enable-misched' the default? Phil -------------- next

Greeting. I am working on one DSA related project. Got several questions about LLVM's DSA analysis: 1. I looked through the llvm doc, it seems "-ds-aa" option is the one I should use. (http://llvm.org/docs/AliasAnalysis.html#the-ds-aa-pass). however based on the poolalloc's svn history, this option was removed on (or before) 2011. May I know why this one was removed ? and is

On 5/19/13 11:46 AM, Jing Zhou wrote: > Greeting. > > I am working on one DSA related project. Got several questions about > LLVM's DSA analysis: > > 1. I looked through the llvm doc, it seems "-ds-aa" option is the one > I should use. > (http://llvm.org/docs/AliasAnalysis.html#the-ds-aa-pass). however > based on the poolalloc's svn history, this

On Sep 25, 2013, at 11:03 PM, Liu Xin <navy.xliu at gmail.com> wrote: > > > > On Wed, Sep 25, 2013 at 1:15 PM, Andrew Trick <atrick at apple.com> wrote: > > On Sep 24, 2013, at 7:59 PM, Liu Xin <navy.xliu at gmail.com> wrote: > >> Hi, Andrew, >> >> Thank you for answering my question. >> >> What's the status of

On Wed, Sep 25, 2013 at 1:15 PM, Andrew Trick <atrick at apple.com> wrote: > > On Sep 24, 2013, at 7:59 PM, Liu Xin <navy.xliu at gmail.com> wrote: > > Hi, Andrew, > > Thank you for answering my question. > > What's the status of misched? is it experimental? I found it is disabled > by default for all architectures(3.4svn). I also don't understand

I overrode getInstrLatency and did some printing to see what is available there. It looks like the registers are still virtual at that point when getInstrLatency is called - is that correct? (we needed to make some decisions based on actual registers that have been assigned since some registers are reserved as address space pointers and we could vary the latency based on which address space

Dear Developers, In current implementation of validity method, objects are first coerced to superclass (slots are striped). Thus, it is not possible to write validity method which would perform some checks on children slots. Say, I want to check if number of slots in a class is equal to "n": setClass("A", representation(a="numeric", n="integer"),

Hi all, I meet this problem when compiling the TREAM benchmark ( http://www.cs.virginia.edu/stream/FTP/Code/) with enable-misched The small function will be scheduled as good code, but if opt inline this function, the inline part will be scheduled as bad code. so I rewrite a simple code as attached link (foo.c), and compiled with two different methods: *method A:* *$clang -O3 foo.c -static -S

Hi, Andrew, Thank you for answering my question. What's the status of misched? is it experimental? I found it is disabled by default for all architectures(3.4svn). I also don't understand the algorithm. Could you point to me more papers or text materials about your approach? it seems that you want to balance register pressure and ILP in misched. On Tue, Sep 24, 2013 at 4:07 PM,

On Sep 24, 2013, at 7:59 PM, Liu Xin <navy.xliu at gmail.com> wrote: > Hi, Andrew, > > Thank you for answering my question. > > What's the status of misched? is it experimental? I found it is disabled by default for all architectures(3.4svn). I also don't understand the algorithm. Could you point to me more papers or text materials about your approach? it seems

Hi Phil. You more or less answered your own question, but let me give you some more info. Maybe it is of use. >From what I understand the SchedMachineModel is the future, although it is not as powerful as itineraries at present. The mi-scheduler is mostly developed around out-of-orders cores, I believe (I love to hear arguments on the contrary). Some of the constraints that can be found in

I am observing poor instruction scheduling in my out-of-tree target. The problem is an over-constrained scheduling DAG. In particular, the DAG includes spurious output dependencies on physical, non-register-allocatable registers. MISched already includes code to avoid this problem. However that code relies on information clobbered by the earlier pass LiveVariables. I wonder whether this is a

On Oct 14, 2013, at 3:27 AM, Zakk <zakk0610 at gmail.com> wrote: > Hi all, > I meet this problem when compiling the TREAM benchmark (http://www.cs.virginia.edu/stream/FTP/Code/) with enable-misched > > The small function will be scheduled as good code, but if opt inline this function, the inline part will be scheduled as bad code. A bug for this is welcome. Pretty soon, I’ll

Hi Andy, thanks for your help!! The scheduled code by method A is same as B when using the new machine model. it's make sense, but there is the another problem, the scheduled code is badly. load/store instruction always reuse the same register Source: #define N 2000000 static double b[N], c[N]; void Scale () { double scalar = 3.0; for (int j=0;j<N;j++) b[j] =

> On Jul 28, 2016, at 1:52 PM, Krzysztof Parzyszek <kparzysz at codeaurora.org> wrote: > > On 7/28/2016 3:49 PM, Matthias Braun wrote: >> >> The isDead and isUndef flags however are required to be correct. > > Undef yes, but what relies on isDead being accurate (before live interval computation)? I only remember Andy/Quentin making those conservative correctness

Hello to all. When studying forums and mailing lists it seems to me that llvm usage for very small arm v6m targets is not so common. In the last months, I have spent some time on analyzing performance of llvm/clang for very small targets. My main objective was to get the best possible performance from portable (non-assembly) crypto numerics for cortex-M0(+) targets. As a result (crypto

On Jun 24, 2013, at 2:47 AM, Chandler Carruth <chandlerc at google.com> wrote: > > On Mon, Jun 24, 2013 at 2:41 AM, Andrew Trick <atrick at apple.com> wrote: > I'm briefly enabling the MachineScheduler pass for x86 tonight to collect information on any failures that may show up. > > To properly enable the new scheduler, this hook is implemented in X86Subtarget:

On Feb 21, 2013, at 9:11 AM, Jonas Paulsson <jonas.paulsson at ericsson.com> wrote: > Hi, > > I am trying to add Hazard scheduling nodes after buildSchedGraph(), with a scheduler derived from ScheduleDAGInstrs. I get weird errors, so I wonder what I am doing wrong? > > What I am doing right now is: > > I have a created MI with opcode HAZARD that does not have

On Oct 15, 2013, at 9:28 PM, Zakk <zakk0610 at gmail.com> wrote: > Hi Andy, thanks for your help!! > The scheduled code by method A is same as B when using the new machine model. > it's make sense, but there is the another problem, the scheduled code is badly. > > load/store instruction always reuse the same register I filed PR17593 with this information. However, I