similar to: Receiving LLVM Error in Custom Backend

Is there an established way of disabling a DAG combine on a per target basis, where it appears to be detrimental to the generated code? Writing if (!mytarget) in DAGCombiner.cpp works but tends to be erased by git merge and generally doesn't look ideal. Writing the inverse transform in target specific code doesn't work in this instance and in general creates an infinite loop. Guidance

But isn't kinda silly that we transform to xor and then we transform it back. What is the advantage in doing so? Also, since we do that method, I now have to introduce setcc patterns for i1 values, instead of being able to just use logical pattern operators like not. -Dilan On Fri, Jul 21, 2017 at 11:00 AM Dilan Manatunga <manatunga at gmail.com> wrote: > For some reason I

Hi, I am having some issues with how some of the instructions are being legalized. So this is my intial basic block. The area of concern is the last three instructions. I will pick and choose debug output to keep this small. SelectionDAG has 36 nodes: t0: ch = EntryToken t6: i32,ch = CopyFromReg t0, Register:i32 %vreg507 t2: i32,ch = CopyFromReg t0, Register:i32 %vreg17

Hi, The following is done on a samba share:- When I want to hide files in on the Windows interface, I right-click the file and check on the hidden attribute, but the file still appears there. Must I rename the file with a dot in front in order to hide it? Any alternative to allow the use of Windows interface to hide it? Thanks. adrian

Hi, Is there a kind of scope mechanism in the instruction lowering pattern language in order to control where instructions are inserted or how they are later reordered during the SelectionDiag linearization? I know the glue chain that stick instructions together. But such mechanism in not provided in instruction lowering pattern. I'm facing many situations where some patterns are lowered into

Hi Krzysztof, Sure, please see below. DAG.dump.() before and after, annotated with what I believe the DAG means. I've spent some time debugging the method but it's proving difficult to determine where the logic is misfiring. Disabling the entire combine causes a lot of failing x86-64 tests - I may have to learn an upstream vector ISA to make progress on this. Thank you >From your

The DAG dumping will try to print some of the nodes "inline" (i.e. where they are used) to make the output more readable, so the dump of the DAG may not strictly reflect the node ordering. -Krzysztof On 5/4/2018 8:18 AM, Dominique Torette via llvm-dev wrote: > Here is a last example to illustrate my concern. > > The problem is about the lowering of node t13. > >

hello: I have 3 data.frame objects. First df object: Of dim (149,31). Columns 2:31 are marked as T1..T14 and N1..N16. Name T1 T2 N1 T3 N2 N3 N4 T4 mu1 10 10 9 10 9 9 8 10 mu2 11 11 9 11 9 9 9 11 ... muN 12 12 9 11 9 9 8 12 Second df object: of Dim (50000,31). Columns 2:31 are maked as T1...T14 and N1..N16.

Here is a last example to illustrate my concern. The problem is about the lowering of node t13. Initial selection DAG: BB#0 '_start:entry' SelectionDAG has 44 nodes: t11: i16 = Constant<0> t0: ch = EntryToken t3: ch = llvm.clp.set.rspa t0, TargetConstant:i16<392>, Constant:i32<64> t5: ch = llvm.clp.set.rspb t3,

Krzysztof, Thanks for your interest to my questions. In order to clarify the context, here is the C source file of my test case. The 3 builtins initialize some stack pointers. They have to be executed before any other instruction. extern float fdivfaddfmul_a(float a, float b, float c, float d); volatile static float x1,x2,x3,x4; void _start(void) { float res;

Have you read http://llvm.org/docs/WritingAnLLVMBackend.html and http://llvm.org/docs/CodeGenerator.html ? http://llvm.org/docs/WritingAnLLVMBackend.html#instruction-selector describes how to define a store instruction. -Eli On 7/6/2017 6:51 PM, hameeza ahmed via llvm-dev wrote: > Please correct me i m stuck at this point. > > On Jul 6, 2017 5:18 PM, "hameeza ahmed"

Hi Teja, > I am new to LLVM and interested in using LLVM to work on a research project for > my Master's degree. > My idea is following - > > 1. I have a simple C program basic.c - > #include <stdio.h> > int main() { > printf("Hello World"); > return 0; > } > > 2. I will generate IR byte code for this basic.c using - > llvm-gcc

Here's our testcase: #include <stdio.h> struct flags { unsigned frog: 1; unsigned foo : 1; unsigned bar : 1; unsigned bat : 1; unsigned baz : 1; unsigned bam : 1; }; int main() { struct flags flags; flags.bar = 1; flags.foo = 1; if (flags.foo == 1) { printf("Pass\n"); return 0; } else {

On 12/21/2016 4:45 PM, Phil Tomson via llvm-dev wrote: > Here's our testcase: > > #include <stdio.h> > > struct flags { > unsigned frog: 1; > unsigned foo : 1; > unsigned bar : 1; > unsigned bat : 1; > unsigned baz : 1; > unsigned bam : 1; > }; > > int main() { > struct flags flags; > flags.bar = 1; >

Question for 'experts' in LP using R (using the lpSolve package, say) -- which does not apply to me for the sort of problem I describe below. I've run any number of LP's using lpSolve in R, but all of them to date have objective and constraint functions that both contain the same variables. This lets you set up a LHS and RHS matrix/vector that are symmetrical. But, for a

Hi, Within a basic block I can remove unnecessary register copies + zero sign extensions of unsigned-8bit-loaded values by implementing isZExtFree() for ISD::LOAD nodes. ...But not between basic blocks. The first block does a CopyFromReg of the unsigned-8bit-loaded vreg1 into a new vreg2. The second block then does a unnecessary zext to vreg2. What I want is the 2nd block to use the original

Hi everyone, I am trying to accomplish a small task that is giving me quite a headache. I would like to automatically generate a series of matrices and give them successive names. Here is what I thought at first: t1<-matrix(0, nrow=250, ncol=1) for(i in 1:10){ t1[i]<-rnorm(250) } What I intended was that the loop would create 10 different matrices with a single column of 250

Apart from the fact that the statement "such that t1+t2+t3+t4=2970 (as it must)" is not correct, the LP can be implemented as follows: library(lpSolve) LHS <- rbind( c(0,0,0,0, 1, 0, 0,0), c(1,0,0,0,-1, 1, 0,0), c(0,1,0,0, 0,-1, 1,0), c(0,0,1,0, 0, 0,-1,1), cbind(-diag(4),diag(4)), c(0,0,0,0,0,1,0,0), c(0,0,0,0,0,0,1,0), c(0,0,0,0,0,0,0,1) ) RHS <-

Hello, i am experimenting with the increase in register/ vector width to 64 elements of 32 bits instead of 16 in x86 backend. for eg. i have a loop with 65 iterations; if my IR generates v64i32 and 1 scalar, still the backend breaks the v64i32 into 4 v16i32. i want it to retain v64i32. like if there are 128 elements in loop then it should break it into 2 v64i32 instructions. in order to do this i

Hi, I am new to LLVM and interested in using LLVM to work on a research project for my Master's degree. My idea is following - 1. I have a simple C program basic.c - #include <stdio.h> int main() { printf("Hello World"); return 0; } 2. I will generate IR byte code for this basic.c using - llvm-gcc -emit-llvm -S basic.c This will give me basic.s which has IR byte code