similar to: [3.9 Release] Please write release notes!

Displaying 20 results from an estimated 6000 matches similar to: "[3.9 Release] Please write release notes!"

2016 Sep 30
4
(Thin)LTO llvm build
I just built a stage-1 compiler from the 3.9 release bits and built the lldb from head sources which worked fine. Let me try again using 3.9 build compiler to build 3.9 bits. Teresa On Tue, Sep 27, 2016 at 2:55 PM, Teresa Johnson <tejohnson at google.com> wrote: > > > On Tue, Sep 27, 2016, 2:38 PM Carsten Mattner <carstenmattner at gmail.com> > wrote: > >> On
2016 Dec 20
6
(Thin)LTO llvm build
​Hi again, Teresa. Looks like I had forgotten to report back with success when finally building 3.9.0 in ThinLTO linker mode back in October. Sorry about that and thanks for helping me out. I know how important it is to get success reports as well, as a developer myself, so sorry again :(. While that worked back then, last weekend I tried to build 3.9.1 using 3.9.0 as installed from Arch Linux
2016 Sep 27
2
(Thin)LTO llvm build
On Tue, Sep 27, 2016 at 6:33 PM, Teresa Johnson <tejohnson at google.com> wrote: > > I can't reproduce the failure. I am building with a clang built > Release from recent source as my stage-1 bootstrap compiler: > clang version 4.0.0 (trunk 282322) (llvm/trunk 282341) The clang I use was built from the 3.9 release branch: clang version 3.9.1 (branches/release_39
2016 Oct 04
0
(Thin)LTO llvm build
On Tue, Oct 4, 2016 at 10:15 AM, Carsten Mattner <carstenmattner at gmail.com> wrote: > On Tue, Oct 4, 2016 at 2:22 AM, Xinliang David Li <xinliangli at gmail.com> > wrote: > > For clang build, cmake flags: > > > > -DCMAKE_EXE_LINKER_FLAGS=-fuse-ld=gold \ > > -DCMAKE_MODULE_LINKER_FLAGS=-fuse-ld=gold \ > >
2020 Oct 12
3
MemorySSA LLVM-dev meeting notes and upcoming meetings
Hello, Following up on last week's LLVM-Dev meeting where we discussed MemorySSA related topics, I created the following google doc <https://docs.google.com/document/d/1-uEEZfmRdPThZlctOq9eXlmUaSSAAi8oKxhrPY_lpjk/edit#> with some of the meeting notes and planning for future meetings. For those who participated, please feel free to add items I may have missed into the document and cc
2016 Sep 10
6
(Thin)LTO llvm build
I tried building llvm, clang, lld, lldb from the 3.9 svn release branch with LTO, and some of the results were unexpected. I first tried to rebuild llvm with llvm-3.9, which has ThinLTO, by providing -DLLVM_ENABLE_LTO=Thin, but that failed very quickly, so I fell back to building with -DLLVM_ENABLE_LTO=On and using the system CC/CXX (gcc 6.1). The resulting installed build is many times bigger
2016 Dec 27
2
3.9 regression with legacy static assert macros (bad type resolution)
It already shipped AFAIK: http://releases.llvm.org/download.html — Mehdi > On Dec 27, 2016, at 9:55 AM, Akira Hatanaka via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Can we still check patches into 3.9.1? > >> On Dec 24, 2016, at 1:47 AM, Jeremy Huddleston Sequoia <jeremyhu at apple.com> wrote: >> >> >>> On Dec 23, 2016, at 11:17,
2016 Dec 27
3
3.9 regression with legacy static assert macros (bad type resolution)
+Tom : is there a plan for a 3.9.2? — Mehdi > On Dec 27, 2016, at 10:30 AM, Mehdi Amini <mehdi.amini at apple.com> wrote: > > It already shipped AFAIK: http://releases.llvm.org/download.html > > — > Mehdi > >> On Dec 27, 2016, at 9:55 AM, Akira Hatanaka via llvm-dev <llvm-dev at lists.llvm.org> wrote: >> >> Can we still check patches into
2016 Sep 27
4
(Thin)LTO llvm build
On Tue, Sep 27, 2016 at 6:53 AM, Mehdi Amini <mehdi.amini at apple.com> wrote: > > > > On Sep 27, 2016, at 2:18 AM, Carsten Mattner <carstenmattner at gmail.com> > wrote: > > > >> On Mon, Sep 26, 2016 at 11:02 PM, Teresa Johnson <tejohnson at google.com> > wrote: > >> I'll either need to get a reproducer from you and/or try to repro
2016 Aug 01
3
testing a back-end pre-emit pass
Hi, Does anyone have any direction for me on testing a back-end pre-emit pass independently of other passes? The pass I'm looking at is a MachineFunctionPass, so the code is already using target-specific instructions. What I'm really looking to do is to see that the pass is correctly converting certain target-specific instructions sequences into other sequences, but I'm unsure how I
2016 Dec 24
2
3.9 regression with legacy static assert macros (bad type resolution)
> On Dec 23, 2016, at 11:17, Frédéric Riss <friss at apple.com> wrote: > > >> On Dec 22, 2016, at 9:36 PM, Jeremy Huddleston Sequoia via llvm-dev <llvm-dev at lists.llvm.org> wrote: >> >> 3.9.0 and current release_39 (r90413) have issues with older static assertion macros like this one from an older libunwind: >> >> #define
2016 Dec 27
0
3.9 regression with legacy static assert macros (bad type resolution)
Can we still check patches into 3.9.1? > On Dec 24, 2016, at 1:47 AM, Jeremy Huddleston Sequoia <jeremyhu at apple.com> wrote: > > >> On Dec 23, 2016, at 11:17, Frédéric Riss <friss at apple.com> wrote: >> >> >>> On Dec 22, 2016, at 9:36 PM, Jeremy Huddleston Sequoia via llvm-dev <llvm-dev at lists.llvm.org> wrote: >>>
2016 Dec 23
0
3.9 regression with legacy static assert macros (bad type resolution)
> On Dec 22, 2016, at 9:36 PM, Jeremy Huddleston Sequoia via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > 3.9.0 and current release_39 (r90413) have issues with older static assertion macros like this one from an older libunwind: > > #define COMPILE_TIME_ASSERT( expr ) \ > extern int compile_time_assert_failed[ ( expr ) ? 1 : -1 ] __attribute__( (
2017 Jan 23
2
3.9 regression with legacy static assert macros (bad type resolution)
There's a regression in AMDGPU which would be nice to get resolved, see: https://bugs.freedesktop.org/show_bug.cgi?id=99078 https://bugs.launchpad.net/ubuntu/+source/llvm-toolchain-3.9/+bug/1656620?comments=all I think it's reasonably low-risk to back-port AMDGPU: Reduce the duration of whole-quad-mode AMDGPU: Do not clobber SCC in SIWholeQuadMode since they've been in trunk and
2015 Sep 18
5
multiply-accumulate instruction
I'm trying to define a multiply-accumulate instruction for the LEON processor, a Subtarget of the Sparc target. The documentation for the processor is as follows: === To accelerate DSP algorithms, two multiply&accumulate instructions are implemented: UMAC and SMAC. The UMAC performs an unsigned 16-bit multiply, producing a 32-bit result, and adds the result to a 40-bit accumulator made
2015 Sep 21
2
multiply-accumulate instruction
I've been looking to see if there's a way to get the instruction below (SMAC) emitted from a higher-level construct, but I'm starting to think this is unrealistic. To do so, I'd have to tie-in two other instructions: Firstly, clearing the ASR18 and Y register somewhere near the start of the method, then copying out the value of these registers somewhere near the end of the method,
2015 Sep 08
4
Inserting MachineInstr's
Hi, I have a task to complete and I'm getting stuck. I can't find anything comparable in the documentation. The shortest explanation I can give is as follows: I need to use double-precision floating point values for floating-point multiplies. I'll not go into why: That would take the discussion away from the essential problem. E.g. Replace: fmuls %f20,%f21,%f8 with the
2016 Dec 23
2
3.9 regression with legacy static assert macros (bad type resolution)
3.9.0 and current release_39 (r90413) have issues with older static assertion macros like this one from an older libunwind: #define COMPILE_TIME_ASSERT( expr ) \ extern int compile_time_assert_failed[ ( expr ) ? 1 : -1 ] __attribute__( ( unused ) ); I notice that the issue is fixed on current trunk. Does anyone know what revision introduced the fix? Can we get it
2016 Aug 03
2
[3.9 Release] Please write release notes!
On 3 August 2016 at 10:46, Renato Golin <renato.golin at linaro.org> wrote: > We certainly do. This is a big deal. I'll write up something and let > Dmitry correct my mistakes. :) Done. > We'll also add the ARM/AArch64 changelogs. Done. :) cheers, --renato
2016 Oct 19
4
[Sparc] vararg double issue on 32 bit Sparc processors
Hi, I've discovered a problem on Sparc processors (specifically, LEON, but I suspect but can't verify that it also happens on all Sparc processors). The problem is, or appears to be with using double values in Sparc (32 bit). Specifically, double values are not being loaded into registers correctly within a function using va_args. Only half the value is loaded (i.e. 32, rather than 64