similar to: testing a back-end pre-emit pass

Hi, I've discovered a problem on Sparc processors (specifically, LEON, but I suspect but can't verify that it also happens on all Sparc processors). The problem is, or appears to be with using double values in Sparc (32 bit). Specifically, double values are not being loaded into registers correctly within a function using va_args. Only half the value is loaded (i.e. 32, rather than 64

The following code is causing me problems in the Sparc back-end and I believe it's related to a lot of issues that I have, so I'd love to work out what I need to do to resolve this. I'm currently not making much headway into it. I'm going to try to simplify this to the core problem I can see and hope I haven't missed anything relevant. The original code I have is as follows:

Hi, I'm trying to implement __builtin_setjmp / __builtin_longjmp for Sparc processors. I think I'm very close, but I can't work out how to issue BuildMI-type instructions to load the address of the recovery location (set in setjmp) into a register using the SETHI / OR combination. I can't see any equivalent code anywhere else in Sparc. I imagine this is similar if I try to make a

I'm trying to define a multiply-accumulate instruction for the LEON processor, a Subtarget of the Sparc target. The documentation for the processor is as follows: === To accelerate DSP algorithms, two multiply&accumulate instructions are implemented: UMAC and SMAC. The UMAC performs an unsigned 16-bit multiply, producing a 32-bit result, and adds the result to a 40-bit accumulator made

Hi, I have a task to complete and I'm getting stuck. I can't find anything comparable in the documentation. The shortest explanation I can give is as follows: I need to use double-precision floating point values for floating-point multiplies. I'll not go into why: That would take the discussion away from the essential problem. E.g. Replace: fmuls %f20,%f21,%f8 with the

I've been looking to see if there's a way to get the instruction below (SMAC) emitted from a higher-level construct, but I'm starting to think this is unrealistic. To do so, I'd have to tie-in two other instructions: Firstly, clearing the ASR18 and Y register somewhere near the start of the method, then copying out the value of these registers somewhere near the end of the method,

Hi, in section B.29. (Write State Register Instructions) of 'The SPARC Architecture Manual Version 8' it is said that the "The write state register instructions are delayed-write instructions." The Y-register is a state-register. Furthermore in the B.29-secion there is a programming note saying: MULScc, RDY, SDIV, SDIVcc, UDIV, and UDIVcc implicitly read the Y register.

Dear everyone, It's time for the release notes nagging email. We have release notes for LLVM, Clang, clang-tools-extra, lld, and Polly. (If there are more, please let me know.) Most of these are pretty empty files; see e.g. the LLVM one at [1]. The internet does read these notes when we release, so please help make them informative! If you made any interesting changes during the past six

On Tue, Sep 18, 2007 at 06:41:38PM +1000, Emil Mikulic wrote: > The "make check" produced: > === Summary === > > # of expected passes 2209 > # of unexpected failures 41 > # of expected failures 5 > gmake[1]: *** [check-local] Error 1 > gmake[1]: Leaving directory `/home/emil/ll/objdir-llvm/test' > gmake: ***

Dear All, I'm trying to emit one of the multi-byte NOP sequences for x86. Any one of the following NOP encodings will do: 0x66 0x90 0x0f 0x1f 0x00 0x0f 0x1f 0x40 0x00 In LLVM 3.1, there doesn't seem to be a multi-byte NOP in the TD files. Is there a way to get a MachineFunctionPass to emit one of these sequences (or to just tell it to emit a certain byte sequence into the code

On 2020-07-13 05:09, Kay Diederichs wrote: > On 7/13/20 4:04 AM, Frank M. Ramaekers Jr. wrote: >> Since I upgraded to CentOS8, I cannot get HandBrakeCLI to work: I could not get HandBrake to work under CentOS 8, so I installed it under Zorin 15 (an Ubuntu-derived German distro). There, it works great. I did not try any of the other distros derived from Debian or Ubuntu itself. Todd

I investigated the MachineFunctionPass (that is runOnMachineFunction, I believe). In my experimentation it didn't seem that the MachineFrameInfo was populated (it consistently said that the stack depth was 0, for example). I might have been doing something wrong? On Fri, Jul 8, 2011 at 5:21 PM, John Criswell <criswell at illinois.edu> wrote: > On 7/8/11 4:09 PM, Andrew Ruef wrote:

I want to create share memory in my MachineFunctionPass, and insert load/store instruction for it. The way to create share memory is to add global variables which are in share memory address space (not sure if it is the only way). Therefore, I should add global variables in fixed size in doInitialization, and record its real size in other place like MachineModuleInfo. Then modify or query its real

Hi All, I'm trying to run multiple instances ( 2 ) of Apache on a single IP address. I need this because I need the two instances to run as different users. I've set up two config files with the following: config-1 config-2 ServerRoot "/etc/httpd" ServerRoot "/etc/httpd" Listen 10.220.1.156:80

Hello everyone, I have written several complex passes till now, but I cannot write a MachineFunctionPass pass. It just gives me segfault. Hence I reduced the pass to the following form : using namespace llvm; namespace { class CFGexplorator : public MachineFunctionPass { public: static char ID; // Pass identification, replacement for typeid CFGexplorator() : MachineFunctionPass(ID)

OK. I know what you mean......... Simply speaking, I want to do some optimizations for PTX, and the information I need is similar to a register allocator. I know PTX is virtual ISA, but I will use PTX as the input of the simulator, gpgpu-sim, so it makes sense. Whether to insert shared memory is depend on the analysis that needs LiveAnalysis, PTX InstrInfo, PTX RegisterInfo, etc. That's why I

Hello, I want to add assembly instructions at certain points in a function. This is X86 specific. So I am working in the lib/Target/X86 folder. I create a `MachineFunctionPass` in that folder. I register it in the X86TargetMachine.cpp in addPreEmitPass(). I use BuildMI to insert my own assembly instructions in the MachineFunctionPass. This works and my assembly instructions are inserted at

On Wed, Sep 19, 2007 at 05:24:12PM +1000, Emil Mikulic wrote: > http://goanna.cs.rmit.edu.au/~emil/llvm2.1-check-debug.txt Here's an ARM test that cores: $ llvm-as < /home/emil/ll/llvm-2.1/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll | llc -march=arm -mattr=+v6,+vfp2 Segmentation fault (core dumped) $ gdb `which llc` llc.core [...] (gdb) where #0 0x0853d606 in

Micah, As you expected, I am trying to create local memory but in the NVPTX backend. It's really not convenient that I can't create local memory in runOnMachineFunction. Hmm.... Since I should do it at doInitialization stage, I also need to do some tricks in global variable and AsmPrinter to resize it. Did you use the similar way? Antony 2013/8/5 Micah Villmow <micah.villmow at

Micah, Thanks for your help. I will study on that code. Justin, Sorry for my misleading word. Local memory in OpenCL is the same as share memory in CUDA. What I mean is share memory, so MachineFrameInfo is not suitable to me. And I need codegen data, so FunctionPass is also not suitable. Anyway, thanks for the suggestion. Antony 2013/8/5 Justin Holewinski <justin.holewinski at