similar to: Finding caller-saved registers at a function call site

Displaying 20 results from an estimated 4000 matches similar to: "Finding caller-saved registers at a function call site"

2016 Jun 22
0
Finding caller-saved registers at a function call site
Hi Rob, Rob Lyerly via llvm-dev wrote: > I'm looking for a way to get all the caller-saved registers (both the > register and the stack slot at which it was saved) for a given function > call site in the backend. What's the best way to grab this > information? Is it possible to get this information if I have the > MachineInstr of the function call? I'm currently
2016 Jun 27
3
Finding caller-saved registers at a function call site
Hi Sanjoy, I'm having trouble finding caller-saved registers using the RegMask operand you've mentioned. As an example, I've got a C function that looks like this: double recurse(int depth, double val) { if(depth < max_depth) return recurse(depth + 1, val * 1.2) + val; else return outer_func(val); } As a quick refresher, all "xmm" registers are considered
2016 Jun 27
0
Finding caller-saved registers at a function call site
Ah, I see -- the registers left out of the mask are considered clobbered. Got it! At a high level, I'm interested in finding the locations of all values that are live at a given call site. You can think of it like a debugger, e.g. gdb -- I'd like to be able to unwind the stack, frame by frame, and locate all the live values for each function invocation (i.e., where they are in a
2016 Jun 27
3
Finding caller-saved registers at a function call site
Hi Rob, Robert Lyerly wrote: > At a high level, I'm interested in finding the locations of all values > that are live at a given call site.**You can think of it like a > debugger, e.g. gdb -- I'd like to be able to unwind the stack, frame by > frame, and locate all the live values for each function invocation > (i.e., where they are in a function's stack
2012 Mar 28
2
[LLVMdev] Suboptimal code due to excessive spilling
Hi, I have run into the following strange behavior and wanted to ask for some advice. For the C program below, function sum() gets inlined in foo() but the code generated looks very suboptimal (the code is an extract from a larger program). Below I show the 32-bit x86 assembly as produced by the demo page on the llvm home page ("Output A"). As you can see from the assembly, after
2016 Jun 28
0
Finding caller-saved registers at a function call site
Hi Sanjoy, On Mon, Jun 27, 2016 at 4:05 PM, Sanjoy Das <sanjoy at playingwithpointers.com> wrote: > Hi Rob, > > Robert Lyerly wrote: > > At a high level, I'm interested in finding the locations of all values > > that are live at a given call site.**You can think of it like a > > debugger, e.g. gdb -- I'd like to be able to unwind the stack, frame by >
2013 Jul 19
4
[LLVMdev] SIMD instructions and memory alignment on X86
Hmm, I'm not able to get those .ll files to compile if I disable SSE and I end up with SSE instructions(including sqrtpd) if I don't disable it. On Thu, Jul 18, 2013 at 10:53 PM, Peter Newman <peter at uformia.com> wrote: > Is there something specifically required to enable SSE? If it's not > detected as available (based from the target triple?) then I don't think
2017 Mar 01
2
[Codegen bug in LLVM 3.8?] br following `fcmp une` is present in ll, absent in asm
Hi, We seem to have found a bug in the LLVM 3.8 code generator. We are using MCJIT and have isolated working.ll and broken.ll after middle-end optimizations -- in the block merge128, notice that broken.ll has a fcmp une comparison to zero and a jump based on that branch: merge128: ; preds = %true71, %false72 %_rtB_724 = load %B_repro_T*, %B_repro_T**
2012 Apr 05
0
[LLVMdev] Suboptimal code due to excessive spilling
I don't know much about this, but maybe -mllvm -unroll-count=1 can be used as a workaround? /Patrik Hägglund -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Brent Walker Sent: den 28 mars 2012 03:18 To: llvmdev Subject: [LLVMdev] Suboptimal code due to excessive spilling Hi, I have run into the following strange behavior
2012 Jan 13
2
[LLVMdev] Odd weak symbol thing on i386
Hi, I'm compiling lldiv.c from the NetBSD standard library. It works on ARM, Mips, Microblaze,ppc, ppc64, and x86_64. On i386 a very strange thing happens. Here's the source: #include <stdlib.h> #define __weak_alias(sym) __attribute__ ((weak, alias (#sym))) lldiv_t lldiv(long long int num, long long int denom) __weak_alias(_lldiv); lldiv_t _lldiv(long long num, long
2017 Jan 09
5
RFC: Dynamically Allocated "Callee Saved Registers" Lists
Dynamically Allocated "Callee Saved Registers" Lists Each Calling convention (CC) defines a static list of registers that should be preserved by a callee function. All other registers should be saved by the caller. Some CCs use additional condition: If the register is used for passing/returning arguments - the caller needs to save it - even if it is part of the Callee Saved Registers
2017 Jan 11
2
RFC: Dynamically Allocated "Callee Saved Registers" Lists
Hi Mehdi, I wasn’t familiar with IPRA before, thank you for bringing it up. After studying it, I have to say that IPRA is a wonderful idea and is well implemented. I tried to reuse the mechanism for the last couple of days. I implemented a solution using IPRA mechanism and encountered few issues: 1. IPRA uses immutable analysis pass called “PhysicalRegisterUsageInfo”. The usage of such
2012 Jan 04
1
[LLVMdev] How can I compile a c source file to use SSE2 Data Movement Instructions?
I write a small function and test it under clang and gcc, filet test.c: double X[100]; double Y[100]; double DA = 0.3; int f() { int i; for (i = 0; i < 100; i++) Y[i] = Y[i] - DA * X[i]; return 0; } clang -S -O3 -o test.s test.c -march=native -ccc-echo result: "D:/work/trunk/bin/Release/clang.exe" -cc1 -triple i686-pc-win32 -S -disable-fr e -disable-llvm-verifier
2015 Jul 30
2
[LLVMdev] [3.7.0] Two late issues with cross compilation to mips
To reduce memory consumption clobbered registers are handled with RegisterMask machine operands which contain a bitset of all registers clobbered. - Matthias > On Jul 29, 2015, at 3:00 PM, Daniel Sanders <daniel.sanders at imgtec.com> wrote: > > I believe I've identified the problem with almabench but I haven't found the root cause in the compiler yet. > > The
2014 Oct 13
2
[LLVMdev] Unexpected spilling of vector register during lane extraction on some x86_64 targets
Hello, Depending on how I extract integer lanes from an x86_64 xmm register, the backend may spill that register in order to load scalars. The effect was observed on two targets: corei7-avx and btver1 (I haven't checked other targets). Here's a test case with spilling/no-spilling code put on conditional compile: #if __SSE4_1__ != 0 #include <smmintrin.h> #else #include
2017 Jan 12
2
RFC: Dynamically Allocated "Callee Saved Registers" Lists
Hi Mehdi, It is true that both IPRA and the proposed mechanism save RegMasks. So you might say that the data structure in the immutable pass should be reused, but this is the only similarity. Even this similarity is not exactly true. I save register masks that doesn’t use passed/returned arguments while IPRA saves register masks for modified registers. So how can they share the same mechanism?
2017 Jan 12
2
RFC: Dynamically Allocated "Callee Saved Registers" Lists
Hi Mehdi, I think that the subject of the RFC is misleading. The true problem that we are trying to solve is to remove returned/passed arguments from the regmask (According to the calling convention). IPRA and CC updated RegMask can’t use the same mechanism because they contradict each other. I think that the following analog will help to explain why I think that a reuse is redundant: Let’s
2016 Oct 12
4
[test-suite] making polybench/symm succeed with "-Ofast" and "-ffp-contract=on"
On Wed, Oct 12, 2016 at 10:53 AM, Hal Finkel <hfinkel at anl.gov> wrote: > I don't think that Clang/LLVM uses it by default on x86_64. If you're using -Ofast, however, that would explain it. I recommend looking at -O3 vs -O0 and make sure those are the same. -Ofast enables -ffast-math, which can legitimately cause differences. > The following tests pass at "-O3" and
2017 Jan 12
2
RFC: Dynamically Allocated "Callee Saved Registers" Lists
Here in an example that explains the difference. // Only declaration – No implementation // Assume that the value is returned in EAX and the arguments are passed in EAX, ECX, EDX, ESI, EDI. int __regcall callee (int a, int b, int c, int d, int e); // implemented in a different module void caller() { … x = callee(1,2,3,4,5); … } What will be RegMask using IPRA register usage collector? Callee
2015 Jul 30
0
[LLVMdev] [3.7.0] Two late issues with cross compilation to mips
Thanks. This is making a lot more sense now and it's looking like this issue isn't Mips specific. Here's the IR dump before simple register coalescing (note: I've patched the IR printer to print the contents of the regmask): 4480B %vreg260<def> = LDC1 %vreg253, <cp#3>[TF=6]; mem:LD8[ConstantPool] AFGR64:%vreg260 GPR32:%vreg253 4496B %vreg261<def> = FMUL_D32