similar to: Is addrspace info available during instruction scheduling?

On Apr 26, 2013, at 3:53 AM, Martin J. O'Riordan <Martin.ORiordan at movidius.com> wrote: > I am migrating the llvm/clang derived compiler for our processor from the > v3.1 to v3.2 codebase. This has mostly gone well except that instruction > latency scheduling is no longer happening. > > The people who implemented this previously sub-classed 'ScheduleDAGInstrs'

On Tue, Nov 17, 2015 at 11:15 AM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > On 11/17/2015 12:26 PM, Rail Shafigulin wrote: > >> >> I tried setting >> let mayLoad = 1 { >> class InstrLD .... { >> } >> } >> >> But that didn't seem to work. When I looked at the debug output the >> latency for the load

I keep getting this error upon building: > Linking CXX executable ../../bin/opt > ../../lib/libLLVMTarget.so: error: undefined reference to > 'llvm::TargetInstrInfo::getNumMicroOps(llvm::InstrItineraryData > const*, llvm::MachineInstr const*) const' > ../../lib/libLLVMTarget.so: error: undefined reference to >

On Thu, Jan 7, 2016 at 1:35 PM, Krzysztof Parzyszek <kparzysz at codeaurora.org > wrote: > On 1/7/2016 3:25 PM, Phil Tomson wrote: > >> >> That's better, but now I get: >> >> XSTGInstrInfo.td:902:3: error: In RelAddr: XSTGRELADDR node requires >> exactly 2 operands! >> >> Which makes some sense as XSTGRELADDR is defined as: >> def

On Thu, Jan 7, 2016 at 12:21 PM, Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 1/7/2016 1:55 PM, Phil Tomson via llvm-dev wrote: > >> >> let Uses= [GRP] in { >> def RelAddr : XSTGPseudo< (outs), >> (ins GPRC:$spoff, GPRC:$dst), >>

It it possible to specify an instruction latency in the itinerary through a command line option? We have several options for a hardware divider which have different latencies and it would be nice if I could specify it through a compiler option rather than changing the value in the code and recompiling llvm every time? Any help is appreciated. -- Rail Shafigulin Software Engineer Esencia

On Jun 8, 2012, at 12:52 PM, Marc J. Driftmeyer <mjd at reanimality.com> wrote: > I keep getting this error upon building: > >> Linking CXX executable ../../bin/opt >> ../../lib/libLLVMTarget.so: error: undefined reference to 'llvm::TargetInstrInfo::getNumMicroOps(llvm::InstrItineraryData const*, llvm::MachineInstr const*) const' >>

Hi llvm-dev, I wonder why there is an extra cycle for getOperandLatency. It doesn't seem intuitive. UseCycle = DefCycle - UseCycle + 1; When I read the comments in TargetItinerary.td, it said OperandCycles are optional "cycle counts". They specify the cycle after instruction issue the values which correspond to specific operand indices are defined or read. I thought if

Hi everyone, The MachineLICM pass has a heuristic such that, even in low-register-pressure situations, it will refuse to hoist "cheap" instructions out of loops. By default, when an itinerary is available, this means that all of the defined operands are available in at most 1 cycle. ARM overrides this, and provides this more-customized definition: bool ARMBaseInstrInfo::

Hi all, If you have an out of tree target and use the IfConverter be aware of a new API call "getPredictationCost“ that you might want to implement: After commit r191671: IfConverter: Use TargetSchedule for instruction latencies For targets that have instruction itineraries this means no change. Targets that move over to the new schedule model will be able to use the new

Hello This is a very newbie question on R syntax, but I do not find the answer.... I want to make a selection on an interval say choose Xint in the interval of temperatures 390-399 I tried this syntax Xint<- X[t>=390 && t< 400] typing >XintI get the answer numeric(0) it did not select any object! 'though I verified that there indeed are occrencies of X in this

I overrode getInstrLatency and did some printing to see what is available there. It looks like the registers are still virtual at that point when getInstrLatency is called - is that correct? (we needed to make some decisions based on actual registers that have been assigned since some registers are reserved as address space pointers and we could vary the latency based on which address space

All: Are there any functions out there for selecting all the points in a region of a plot. I envision something like the identify() function except one could circle a cloud of points (and perhaps a vector would be returned of the same length as the points plotted indicating logical membership in the circled cloud). Perhaps someone has done something with the locator() function that would

Hi R experts, I'm trying to use nls() for a piecewise linear regression with the first slope constrained to 0. There are 10 data points and when it does converge the second slope is almost always over estimated for some reason. I have many sets of these 10-point datasets that I need to do. The following segment of code is an example, and sorry for the overly precise numbers, they are just

In our architecture loads from certain memory locations take a long time to complete (on the order of 150 clock cycles). Since we don't have a way to tell at compile time if the address being loaded from lies in slow or fast memory, I've gone ahead and made all of the load numbers high, such as: InstrItinData< II_LOAD1, [InstrStage<150, [AGU]>]>, However, I see that

Hello, I need the expression in string. How can i convert llvm::MCExpr * to string? Please help. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20171005/50817330/attachment.html>

Hi sorta piggybacking on the other thread. I am looking for some feedback on how to implement the following idea in llvm. The really short version of the idea is this: * I want to alloca a field (record/struct), so that its size is an even multiple of 64 bytes. [^1] * This allocaed field will be exclusively used as an argument to functions * llvm should be aware of the extra bytes and should

Dear R-helpers, I'd like to understand how to test the statistical significance of a random effect in gamm. I am using gamm because I want to test a model with an AR(1) error structure, and it is my understanding neither gam nor gamm4 will do the latter. The data set includes nine short interrupted time series (single case designs in education, sometimes called N-of-1 trials in medicine)

Hi all, I'm interested in obtaining the cycles spend by the CPU from LLVM and i was wondering if this was possible to obtain this with the scheduling information from LLVM. (For the cortex-m0 in particular). I found the following function : getInstrLatency() in the TargetInstrInfo class. If i sum the latencies of the instructions in a basic block i suppose i will get the total cycle cost

I am slightly unclear about the semantics of the addrspace attribute and there use with intrinsics. For example, is the following code valid: %ptr = malloc i32 addrspace(11) %result = call i32 @llvm.atomic.load.add.i32( i32 addrspace(11)* %ptr, i32 4); If this is valid it means that a certain amount of type information is lost at the LLVM IL level and if it is not valid, then it is