Displaying 20 results from an estimated 1000 matches similar to: "[GSoC 2016] Parameters of a target architecture"
2015 Jan 14
6
[LLVMdev] Instruction Cost
Hi,
I'm looking for APIs that compute instruction costs, and noticed several of
them.
1. A series of APIs of TargetTransformInfo that compute the cost of
instructions of a particular type (e.g. getArithmeticInstrCost and
getShuffleCost)
2. TargetTransformInfo::getOperationCost
3. CostModel::getInstructionCost::getInstructionCost in
lib/Analysis/CostModel.cpp
Only the first one is used
2016 May 31
2
[GSoC 2016] [Polly] Implementation of tiling, interchanging and unrolling of specific loops based on the algorithm for the analytical modeling
Hi Tobias,
I think that we could split a patch that contains an implementation of
tiling, interchanging and unrolling of specific loops into three
separate patches:
1. The first one adds a class that describes a processor model. It
also adds a new command line parameter that contains all necessary
parameters of a target architecture, which are used to construct
objects of the class.
2. The
2013 Nov 15
4
[LLVMdev] Limit loop vectorizer to SSE
Something like:
index 6db7f68..68564cb 100644
--- a/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -1208,6 +1208,8 @@ void InnerLoopVectorizer::vectorizeMemoryInstruction(Instr
Type *DataTy = VectorType::get(ScalarDataTy, VF);
Value *Ptr = LI ? LI->getPointerOperand() : SI->getPointerOperand();
unsigned Alignment = LI ?
2015 Jan 15
2
[LLVMdev] Instruction Cost
CostModule::getInstructionCost also consults TTI (
http://llvm.org/docs/doxygen/html/CostModel_8cpp_source.html#l00380). No?
Jingyue
On Wed, Jan 14, 2015 at 4:05 PM, Chandler Carruth <chandlerc at google.com>
wrote:
>
> On Wed, Jan 14, 2015 at 3:54 PM, Jingyue Wu <jingyue at google.com> wrote:
>
>> I'm looking for APIs that compute instruction costs, and noticed
2013 Nov 15
0
[LLVMdev] Limit loop vectorizer to SSE
----- Original Message -----
> From: "Arnold Schwaighofer" <aschwaighofer at apple.com>
> To: "Joshua Klontz" <josh.klontz at gmail.com>
> Cc: "LLVM Dev" <llvmdev at cs.uiuc.edu>
> Sent: Friday, November 15, 2013 4:05:53 PM
> Subject: Re: [LLVMdev] Limit loop vectorizer to SSE
>
>
> Something like:
>
> index
2013 Nov 15
2
[LLVMdev] Limit loop vectorizer to SSE
Yes,
I was just about to send out:
DL->getABITypeAlignment(ScalarDataTy);
The question is:
“… ABI alignment for the target …"
is that
getPrefTypeAlignment
or
getABITypeAlignment
I would have thought the latter.
On Nov 15, 2013, at 4:12 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> ----- Original Message -----
>> From: "Arnold Schwaighofer"
2013 Nov 15
0
[LLVMdev] Limit loop vectorizer to SSE
Nadav,
I believe aligned accesses to unaligned pointers is precisely the issue.
Consider the function `add_u8S` before[1] and after[2] the loop vectorizer
pass. There is no alignment assumption associated with %kernel_data prior
to vectorization. I can't tell if it's the loop vectorizer or the codegen
at fault, but the alignment assumption seems to sneak in somewhere.
v/r,
Josh
[1]
2013 Nov 15
6
[LLVMdev] Limit loop vectorizer to SSE
On Nov 15, 2013, at 12:36 PM, Renato Golin <renato.golin at linaro.org> wrote:
> On 15 November 2013 20:24, Joshua Klontz <josh.klontz at gmail.com> wrote:
> Agreed, is there a pass that will insert a runtime alignment check? Also, what's the easiest way to get at TargetTransformInfo::getRegisterBitWidth() so I don't have to hard code 32? Thanks!
>
> I think
2018 Jul 23
2
KNL Vectorization with larger vector width
Thank You.
But I cannot find your mentioned function
LoopVectorizationCostModel::computeFeasibleMaxVF(bool
OptForSize, unsigned ConstTripCount). I am using LLVM 4. I have been trying
to get the required code portion in LoopVectorize.cpp file. But I am unable
to debug this. each time i debug it, it returns me vectorized IR in gdb.
My goal is simple when i mention my target name in opt it should
2017 Feb 08
2
ShuffleKind SK_ExtractSubvector
Hi,
I am a little unsure about the semantics of the ShuffleKind
SK_ExtractSubvector. It seems a subvector is to be extracted, starting
from a given index of a given subtype.
First of all, if index 0 is passed, I suppose this would mean a noop?
But what about calls like the one made of LoopVectorizer for
Instruction::PHI in getInstructionCost():
return
2016 Jan 05
3
TargetTransformInfo getOperationCost uses
Hi,
I'm trying to implement the TTI hooks for AMDGPU to avoid unrolling loops for operations with huge expansions (i.e. integer division).
The values that are ultimately reported by opt -cost-model -analyze (the actual cost model tests) seem to not matter for this. The huge cost I've assigned division doesn't prevent the loop from being unrolled, because it isn't actually
2013 Nov 15
2
[LLVMdev] Limit loop vectorizer to SSE
Agreed, is there a pass that will insert a runtime alignment check? Also,
what's the easiest way to get at TargetTransformInfo::getRegisterBitWidth()
so I don't have to hard code 32? Thanks!
-Josh
On Fri, Nov 15, 2013 at 3:20 PM, Frank Winter <fwinter at jlab.org> wrote:
> Hmm.. I don't quite understand. How can a module validator
> catch this, when it's the
2013 Jan 05
1
[LLVMdev] RFC: Can we make TargetTransformInfo an analysis group?
I know, I said a bad word -- analysis group.
But it works pretty much the way I think we want here. We *always* want a
TargetTransformInfo, and we have reasonable (conservative) stubs in place.
We would just like the option of providing one from the target that has
very clever implementations.
I would propose that we make TargetTransformInfo be an analysis group, and
provide
2015 Jan 19
2
[LLVMdev] Vectorization Cost Models and Multi-Instruction Patterns?
Hi all,
While tinkering with saturation instructions, I hit problems with the
cost model calculations.
The loop vectorizer cost model accumulates the individual TTI cost
model of each instruction. For saturating arithmetic, this is a gross
overestimate, since you have 2 sexts (inputs), 2 icmps + 2 selects
(for the saturation), and a truncate (output); these all fold alway.
With an intrinsic,
2020 Nov 05
4
[Proposal] Introducing the concept of invalid costs to the IR cost model
Hi,
I'd like to propose a change to our cost interfaces so that instead of returning
an unsigned value from functions like getInstructionCost, getUserCost, etc., we
instead return a wrapper class that encodes an integer cost along with extra
state. The extra state can be used to express:
1. A cost as infinitely expensive in order to prevent certain optimisations
taking place. For example,
2013 Jan 20
5
[LLVMdev] Sizeof a type?
Is there a way to get the sizeof a type? Say I've created a struct type without any explicit attribtues, and I want to call malloc() to allocate space for it. Can I get the size as an llvm::Constant* (or other llvm::Value*) given an llvm::StructType* or other llvm::Type*?
TIA,
--
Rick
2013 Nov 15
2
[LLVMdev] Limit loop vectorizer to SSE
A fix for this is in r194876.
Thanks for reporting this!
On Nov 15, 2013, at 3:49 PM, Joshua Klontz <josh.klontz at gmail.com> wrote:
> Nadav,
>
> I believe aligned accesses to unaligned pointers is precisely the issue. Consider the function `add_u8S` before[1] and after[2] the loop vectorizer pass. There is no alignment assumption associated with %kernel_data prior to
2013 Nov 15
0
[LLVMdev] Limit loop vectorizer to SSE
On 15 November 2013 20:24, Joshua Klontz <josh.klontz at gmail.com> wrote:
> Agreed, is there a pass that will insert a runtime alignment check? Also,
> what's the easiest way to get at TargetTransformInfo::getRegisterBitWidth()
> so I don't have to hard code 32? Thanks!
>
I think that's a fair question, and it's about safety. If you're getting
this on the
2015 May 04
3
[LLVMdev] AVX2 Cost Table in X86TargetTransformInfo
Thanks Nadav for the info. It clears my query :)
Yes its an integer ADD, and since AVX2 supports 256 bits integer
arithmetic, so its cost is less than AVX1.
One query though - shouldn't then the cost of integer ADD/SUB/MUL (which
would be 1) be explicitly specified in AVX2 cost table? Because right now
this entry is missing and cost of these operations are taken from BaseTTI
(which is
2018 Jul 23
2
KNL Vectorization with larger vector width
Thank You. I got it. Version issue.
TTI.getRegisterBitWidth(true)
How to put my target machine info in TTI?
Please help.
On Mon, Jul 23, 2018 at 11:33 PM, Friedman, Eli <efriedma at codeaurora.org>
wrote:
> On 7/23/2018 10:49 AM, hameeza ahmed via llvm-dev wrote:
>
> Thank You.
>
> But I cannot find your mentioned function