similar to: LLVM issuse:AArch64 TargetParser

Hi, A64 versus A32/T32 code generation is controlled by the -target option which I don’t believe is under discussion here. James On 18 May 2016, at 13:17, Bruce Hoult <bruce at hoult.org<mailto:bruce at hoult.org>> wrote: Note that armv8a modifies the A32 and T32 instruction sets, and is therefore an important -march option for 32 bit code. Therefore armv8a can not be used to imply

On 5 May 2016 at 13:01, Bradley Smith <Bradley.Smith at arm.com> wrote: > Allowing -march=aarch64/arm64 is somewhat misleading I think, -march is used > for specifying an architecture version to target whereas aarch64/arm64 don’t > convey any information to that effect, does it mean armv8a, armv8.1-a, etc? Hi Bradley, That's a good point. But also, what does "armv8a"

Hi all, Actually,I found there is a same problem for arm.For this case,I think > maybe we can play a trick in the clang. > Checking whether the given arch valid or not,before we throw it to the > parser,which can be used for both arm > and aarch64. For the actions I mentioned above,I wrote a check function as below, basing on the naming rules of the arm architecture. +//Only if

On 8 December 2016 at 02:34, Jojo Ma <jojo.ma at linaro.org> wrote: > It would be profitable as well if we could enable the canonicalisation on > it. > sequence before this canonicalisation (ARM): > test: > .fnstart > @ BB#0: @ %entry > movw r1, #65534 > and r1, r0, r1 > ubfx r0, r0, #1, #15 > add r0, r0, r1, lsr #1 > bx lr

On 19 December 2016 at 09:58, Jojo Ma <jojo.ma at linaro.org> wrote: > /home/likewise-open/SPREADTRUM/jojo.ma/jojoma/source/llvm/llvm-linaro/llvm/llvm/test/CodeGen/Thumb2/machine-licm.ll:88:10: > error: expected string not found in input > ; CHECK: movw {{(r[0-9])|(lr)}}, #32768 > ^ > <stdin>:56:2: note: scanning from here > movw r12, #32768 > ^ Hi

Hi Folks, I'm back looking at the target parser that we discussed last year, and I have some questions. http://lists.cs.uiuc.edu/pipermail/cfe-dev/2014-August/038699.html There is no way I can create a target-independent parser in lib/Target without re-encoding all the information about the targets that we already have in the table-gen files on all targets' directories. Doing that would

On 9 March 2015 at 18:21, Reid Kleckner <rnk at google.com> wrote: > To be clear, TargetParser is about parsing subtarget CPUs and features, > right? In the first stage, yes. But there's a lot more. I hope this ends up being a much larger infrastructure to query for target support, not just parsing strings (which we can cope with duplication), but defining architectural behaviour,

Thanks very much, Renato! I looked into the regressions, there're many cases have similar context as the case I mentioned but N just has only one use. In this case, the canonicalisation won't make it more profitable, will only prevent the possible folding or make the sequence is not expected. The regressions be eliminated, after I limit the expanding to not "N->hasOneUse()".

Hi, Below is a document detailing changes we'd like to make to Clang/LLVM to improve the usability of the target options for ARM and AArch64. To keep things simple the proposed changes are listed at the start and you can find the supporting examples at the end of the document. I look forward to your feedback. Thanks, David Spickett. RFC New Clang target feature selection options for

On 10 March 2015 at 16:20, Mehdi Amini <mehdi.amini at apple.com> wrote: > I’d like to avoid as much as possible adding compilation time to the process unless it is necessary (I’m not saying it does not worth it here). As I said in the review, it may end up being faster, because of the amount of crap we'll remove from all tools and LLVM. > It is not clear to me why do you need

Motivation At the moment, when targeting armv7a, clang defaults to generate code as if -mcpu=cortex-a8 was specified. When targeting armv8a, it defaults to generate code as if -mcpu=cortex-a53 was specified. This leads to surprising code generation, by the compiler optimizing for a specific micro-architecture, whereas the intent from the user was probably to generate code that is

Hi All, I have a problem with VectorLegalizer::ExpandStore() with v4i1. Let's see a example. * LLVM IR store <4 x i1> %edgeMask_for.body1314, <4 x i1>* %27 * SelectionDAG before vector legalization ch = store<ST1[%16](align=4), trunc to v4i1> t0, t128, t32, undef:i64 * SelectionDAG after vector legalization ch = store<ST1[%16](align=4), trunc to i1> t0, t133, t32,

--- celt/arch.h | 5 +++++ silk/macros.h | 4 +--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/celt/arch.h b/celt/arch.h index 9f74ddd..670527b 100644 --- a/celt/arch.h +++ b/celt/arch.h @@ -78,6 +78,11 @@ static OPUS_INLINE void _celt_fatal(const char *str, const char *file, int line) #define UADD32(a,b) ((a)+(b)) #define USUB32(a,b) ((a)-(b)) +/* Set this if opus_int64

Thanks for everyone giving their feedback! I saw pretty unanimous support for making -mcpu=generic the default and making -mcpu=generic schedule for an in-order CPU (Cortex-A8 in this case). I'll be making those changes shortly. I think the comments also make clear that it's less obvious whether we'd want -mcpu=native to become a default. It's probably good for some use cases, but

--- configure.ac | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/configure.ac b/configure.ac index f52d2c2..e1a6e9b 100644 --- a/configure.ac +++ b/configure.ac @@ -190,7 +190,7 @@ AC_ARG_ENABLE([rtcd], [enable_rtcd=yes]) AC_ARG_ENABLE([intrinsics], - [AS_HELP_STRING([--disable-intrinsics], [Disable intrinsics optimizations for ARM(float) X86(fixed)])],, +

Hi All, Can someone comment below question whether it is wrong or not please? 2016-06-25 7:52 GMT+01:00 jingu kang <jaykang10 at gmail.com>: > Hi All, > > I have a problem with VectorLegalizer::ExpandStore() with v4i1. > > Let's see a example. > > * LLVM IR > store <4 x i1> %edgeMask_for.body1314, <4 x i1>* %27 > > * SelectionDAG before vector

Dear R users, I have a data frame with one column (4000 rows) containing name codes (factor with 63 levels). I would like to associate each name with a particular Type (coded as 1,2,3,4,H or H1) in a second column. Is it possible to do a lookup table of associations (i.e. A23 is of type 1, A13 is of type 3 ...) so as to fill up automatically the $Type column. df() $Source $Type A23 A24 A9 A32

Greetings - Has anyone ever managed to install 4.2 on a Sony Vaio desktop, model VGC-RB53 ? I can install either mentioned - but on bottup after the install, I get a kernel panic and it just hangs. For that matter, it does the same if I try FC4 - TIA -- Best regards, Chris Never create a problem for which you do not have the answer.

Default install with local_unbound and ntpd can't be functional with incorrect date/time in BIOS: Unbound requred correct time for DNSSEC check and refuseing queries ("Jul 1 20:17:29 yellowrat unbound: [3444:0] info: failed to prime trust anchor -- DNSKEY rrset is not secure . DNSKEY IN") ntpd don't have any numeric IP of ntp servers in ntp.conf -- only symbolic names like

Default install with local_unbound and ntpd can't be functional with incorrect date/time in BIOS: Unbound requred correct time for DNSSEC check and refuseing queries ("Jul 1 20:17:29 yellowrat unbound: [3444:0] info: failed to prime trust anchor -- DNSKEY rrset is not secure . DNSKEY IN") ntpd don't have any numeric IP of ntp servers in ntp.conf -- only symbolic names like