similar to: [llvm dev] do we have allocator hook to use maximum different registers?

Hi, This is really basic block level pass. It is no difference what is level, problem is the same. After fixing for asm parser, assembler syntax is no more valid for backend, without processing with asm parser. May be it will be solution to process inline asm on insn printer level to remove syntax fixes. But just switch it off without lto will make compiler do less job P.S. sorry for dup,

Hi, Imagine that your backend has valid asm instruction written like this: "%x mnem %y, %z" And user puts it as inline assembler: __asm__ ("%x mnem %y, %z"); It can not be parsed with current llvm asm parser, because it starts with % (moreover it has mnemonic in second place) Say you written pass, that makes it "mnem %x, %y, %z". Now this guy can be parsed, but

Hi, In LTO we have AsmParser that process inline assembler instructions to MCInst and I want to fix some inline assembler in order to conform its rules (do not start with non-identifier and so on) because asm syntax of our backend allows some incompatible patterns. In order to do this I am adding IR-level target-specific pass. But those fixes shall not be applied when there is no AsmParser later

Hi, I want to enable some target-specific functionality only if current build is 2nd LTO stage (i.e. optimizer called from plugin). What is best and recommended way to do it? --- With best regards, Konstantin

Hi, Working on private backend, based on llvm-3.7 Inside lib/Transforms/InstCombine/InstCombineCompares.cpp there is attempt to optimize fabs: if (F->getIntrinsicID() == Intrinsic::fabs || ... switch (I.getPredicate()) { ... case FCmpInst::FCMP_OGT: return new FCmpInst(FCmpInst::FCMP_ONE, CI->getArgOperand(0), RHSC); But CI->getArgOperand(0)

Hi, I am debugging private backend and faced interesting problem: sometimes spill hoisting creates double stores. (some output from -debug-only=regalloc). First hoisting: Checking redundant spills for 0 at 16r in %vreg19 [16r,144B:0)[144B,240B:1)[240B,280r:2)[296r,416B:3)[416B,456r:4)[472r,592B:5) 0 at 16r 1 at 144B-phi 2 at 240B-phi 3 at 296r 4 at 416B-phi 5 at 472r Merged to stack int: SS#0

Hi, Thanks for pointing direction. As far, as I understand by reversing, logic, that I want to overwrite is digged into: lib/MC/MCSectionELF.cpp MCSectionELF::PrintSwitchToSection if (ShouldOmitSectionDirective(SectionName, MAI)) { OS << '\t' << getSectionName() << '\n'; return; } // otherwise print ".section" directive and then section

Hi, In GCC there is one useful option -dp (or -dP for more verbose output) to annotate assembler with instruction patterns, that was used when assembler was generated. For example: double test(long long s) { return s; } gcc -S -dp -O0 test.c test: .LFB0: .cfi_startproc pushq %rbp # 18 *pushdi2_rex64/1 [length = 1] .cfi_def_cfa_offset 16 movq %rsp, %rbp # 19 *movdi_1_rex64/2

On Thu, Mar 15, 2012 at 11:00:54AM +0400, Konstantin Vladimirov wrote: > Hi, > > Thanks for pointing direction. As far, as I understand by reversing, > logic, that I want to overwrite is digged into: > > lib/MC/MCSectionELF.cpp > > MCSectionELF::PrintSwitchToSection > > if (ShouldOmitSectionDirective(SectionName, MAI)) { > OS << '\t'

On 2/16/2016 8:44 AM, Konstantin Vladimirov via llvm-dev wrote: > > CI->getArgOperand(0) returns operand with type (double*) rather then > double, because in our ABI doubles are passed via memory. The LLVM intrinsics in the LLVM IR must conform to whatever the IR's requirements are. That means that even in the case of your backend, the arguments to the intrinsic must be doubles,

Trying to build today's svn on fc5, gcc-4.1.0,amd64: gcc -DHAVE_CONFIG_H -I. -I. -I.. -I../include -I../include -I.. -I/usr/include -O2 -fPIC -funswitch-loops -ftree-loop-linear -march=k8 -ftree-vectorize -pipe -mfpmath=sse -frename-registers -O3 -msse -MT nb_celp.lo -MD -MP -MF .deps/nb_celp.Tpo -c nb_celp.c -fPIC -DPIC -o .libs/nb_celp.o nb_celp.c: In function 'nb_encode':

On 02.03.2012, at 09:20, Konstantin Vladimirov wrote: > Hi, > > In GCC there is one useful option -dp (or -dP for more verbose output) > to annotate assembler with instruction patterns, that was used when > assembler was generated. For example: The internal "-mllvm -show-mc-inst" option is probably as close as you can get. $ clang -S -O0 test.c -mllvm -show-mc-inst -o

I am trying to build FreeBSD update, STABLE branch, and buildkernel apparently snagged on ndis, which I don't want to do without. According to "man ndis", I need in kernel config options NDISAPI device ndis device wlan which I have: device wlan # 802.11 support options NDISAPI # This is in the hope of enabling Hiro USB wireless adapter device

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 I did a cvsup for RELENG_7 earlier today. # uname -a FreeBSD polo.example.org 7.1-STABLE FreeBSD 7.1-STABLE #8: Sat Apr 11 18:50:17 EDT 2009 dan@polo.example.org:/usr/obj/usr/src/sys/PHENOM amd64 No idea what went wrong here. Clues please. cc -c -O2 -frename-registers -pipe -fno-strict-aliasing -std=c99 -g - -Wall -Wredundant-decls

Hi all, I was wondering about whether the PBQP register allocator is likely to be maintained in the future. It's proving to be a nice way to encode some instruction encoding constraints for an out-of-tree backend we have, but there's concern about it being abandoned or bitrotting in the future. Also, if PBQP is likely to lapse out of regular maintenance in the future, is there a simple

Thanks Diana. That is indeed the assumption in the code and this is obviously wrong. Could you try the attached patch? (I haven’t even tried to compile it though) Cheers, -Quentin -------------- next part -------------- A non-text attachment was scrubbed... Name: localizer_tentative_fix.diff Type: application/octet-stream Size: 774 bytes Desc: not available URL:

Thanks Quentin, it's in progress now, I'll let you know how it goes. Cheers, Diana On 27 May 2017 at 03:36, Quentin Colombet <qcolombet at apple.com> wrote: > Hi Kristof, > > I’ve pushed the localizer in r304051 and added it in the AArch64 O0 pipeline > in r304052. > > I let Diana investigate the seg fault she was seeing. > > @Diana, let me know if you need

Hi Kristof, > On May 25, 2017, at 2:09 AM, Kristof Beyls <kristof.beyls at arm.com> wrote: > >> >> On 24 May 2017, at 22:01, Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote: >> >> Hi Kristof, >> >> Thanks for going back so fast! >> >>> On May 24, 2017, at 12:57 PM, Kristof Beyls

Cool test :) It seems to work fine now, I don't see any new failures. IIUC, Kristof is also giving it another run. Cheers, Diana On 30 May 2017 at 22:57, Quentin Colombet <qcolombet at apple.com> wrote: > Hi Diana, > > I’ve actually gone ahead and pushed the fix as I was able to produce a > small reproducer. > > This is r304244 > > Let me know if you encounter

I have a host-parasite association matrix in which parasite species are rows and host species columns and cells contain the frequency of interactions. Some parasites are associated with many hosts, and some hosts harbor several parasites, and I want to repeatedly select only one single representative host per "generalized" (multi-host) parasite to create a new matrix in which no hosts