similar to: How to register a pass as being optional?

Hi, MemDep caches results for local queries and provides means to invalidate them by keeping reverse maps. Unfortunately, it also caches results that represent non-local dependencies, for which there are no reverse map entries, and thus those entries can not be invalidated. This is a problem when an optimization turns a non-local dependency into a local one.

One option may be to prevent the formation of ROTL, if possible, and then generating rol by hand. Marking it as "expand" would likely stop the DAG combiner from creating it. Then you could "preprocess" the selection DAG before the instruction selection and do the pattern matching yourself. -Krzysztof On 11/3/2016 4:24 PM, Phil Tomson via llvm-dev wrote: > I could try

Hi Phil. You more or less answered your own question, but let me give you some more info. Maybe it is of use. >From what I understand the SchedMachineModel is the future, although it is not as powerful as itineraries at present. The mi-scheduler is mostly developed around out-of-orders cores, I believe (I love to hear arguments on the contrary). Some of the constraints that can be found in

I think those should be considered internal options for (llvm codegen) developers, a normal compiler user should not need to use any of them. Of course you can look around the llvm sourcecode (esp. in lib/CodeGen/MachineScheduler.cpp) and see what cl::opt options are available and how they affect the scheduler operation. In case of the MachineScheduler all settings are the same regardless of the

Setting the ISD::ROTL to Expand doesn't work? (via SetOperation) You could also do a Custom hook if that's what you're looking for. On Thu, Nov 3, 2016 at 5:12 PM, Phil Tomson <phil.a.tomson at gmail.com> wrote: > ... or perhaps to rephrase: > > In 3.9 it seems to be doing a smaller combine much sooner, whereas in 3.6 > it deferred that till later in the

On Wed, Dec 2, 2015 at 10:39 AM, David Chisnall <David.Chisnall at cl.cam.ac.uk > wrote: > On 2 Dec 2015, at 18:30, Phil Tomson <phil.a.tomson at gmail.com> wrote: > > > >> If you want to pass LLVM arguments to clang, then you must prefix them > with -llvm (e.g. -mllvm -loops -mllvm lcssa). > > > > > > I just tried this: > > CFLAGS +=

So if I use the SchedMachineModel method, can I just skip itineraries? Phil On Wed, Apr 20, 2016 at 12:29 PM, Sergei Larin <slarin at codeaurora.org> wrote: > Target does make a difference. VLIW needs more hand-holding. For what you > are describing it should be fairly simple. > > > > Best strategy – see what other targets do. ARM might be a good start for > generic

I see that there are several options to influence instruction scheduling, but there doesn't seem to be a lot of information about what they do, for example: -misched-topdown -misched-bottomup The description in MachineScheduler.cpp says: "Force top-down list scheduling" and "Force bottom-up list scheduling" Which isn't too helpful - where might I want to use these?

On Fri, Nov 6, 2015 at 11:10 AM, Tim Northover <t.p.northover at gmail.com> wrote: > On 6 November 2015 at 11:00, Phil Tomson <phil.a.tomson at gmail.com> wrote: > > With 3.6 I get an unused argument warning with -enable-pie: > > > > $ clang -v -emit-llvm -enable-pie -O0 -S global_dat.c -o > > global_dat_x86_pie.ll > > Yes, it's an llc option not a

Hello everyone, I have written several complex passes till now, but I cannot write a MachineFunctionPass pass. It just gives me segfault. Hence I reduced the pass to the following form : using namespace llvm; namespace { class CFGexplorator : public MachineFunctionPass { public: static char ID; // Pass identification, replacement for typeid CFGexplorator() : MachineFunctionPass(ID)

On Fri, Nov 6, 2015 at 10:46 AM, Tim Northover <t.p.northover at gmail.com> wrote: > On 6 November 2015 at 10:32, Phil Tomson via llvm-dev > <llvm-dev at lists.llvm.org> wrote: > > So if I were to pass this .ll file (global_dat_x86_pie.ll) to llc how > would > > llc know that the PIE Level is 2? Is this an oversight, bug, or expetcted > > behaviour with a

On Mon, Aug 22, 2016 at 11:40 AM, Matt Arsenault <arsenm2 at gmail.com> wrote: > > > On Aug 22, 2016, at 11:20, Phil Tomson via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > > > We improved our instruction itineraries and now we're seeing our > testcases for fence instructions break. > > > > For example, we have this testcase: > >

I found that : "Code generator passes are registered and initialized specially by TargetMachine::addPassesToEmitFile and similar routines, so they cannot generally be run from the *opt* or *bugpoint* commands."...So how I can run a MachineFunctionPass? In the end, I just want to apply a DFS on a CFG of a function. And I need oriented edges and wanted to use

On Wed, Dec 2, 2015 at 10:17 AM, David Chisnall <David.Chisnall at cl.cam.ac.uk > wrote: > On 2 Dec 2015, at 17:56, Phil Tomson via llvm-dev <llvm-dev at lists.llvm.org> > wrote: > > > > Now my intent is to figure out which optimization pass is causing the > problem by trying each one until I hit the same problem as with -O1, but > clang itself doesn't seem

I overrode getInstrLatency and did some printing to see what is available there. It looks like the registers are still virtual at that point when getInstrLatency is called - is that correct? (we needed to make some decisions based on actual registers that have been assigned since some registers are reserved as address space pointers and we could vary the latency based on which address space

Is there any way to get it to delay this optimization where it goes from this: Initial selection DAG: BB#0 'bclr64:entry' SelectionDAG has 14 nodes: t0: ch = EntryToken t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0 t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1 t6: i64 = sub t4, Constant:i64<1> t7: i64 = shl Constant:i64<1>, t6

0 down vote favorite <http://stackoverflow.com/questions/34049511/how-to-pass-optimization-passes-to-clang#> I'm trying to debug an issue for a new target where a testcase fails with -O1 optimization and passes with -O0 optimization. I got a list of optimization passes being performed when 'clang -O1' is called like this: llvm-as < /dev/null | opt -O1 -disable-output

We improved our instruction itineraries and now we're seeing our testcases for fence instructions break. For example, we have this testcase: @write_me = external global i32 @read_me = external global i32 ; Function Attrs: nounwind define i32 @xstg_intrinsic(i32 %foo) #0 { entry: ; CHECK: store r0, r1, 0, 32 ; CHECK-NEXT: fence 2 %foo.addr = alloca i32, align 4 store i32 %foo,

On Thu, Jan 7, 2016 at 1:35 PM, Krzysztof Parzyszek <kparzysz at codeaurora.org > wrote: > On 1/7/2016 3:25 PM, Phil Tomson wrote: > >> >> That's better, but now I get: >> >> XSTGInstrInfo.td:902:3: error: In RelAddr: XSTGRELADDR node requires >> exactly 2 operands! >> >> Which makes some sense as XSTGRELADDR is defined as: >> def

Thanks, that worked. So that's basically a cast, then? I have another question about expanding that pseudo op, but I'll post it separately. Phil On Wed, Jan 13, 2016 at 10:26 AM, Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 1/13/2016 11:59 AM, Phil Tomson via llvm-dev wrote: > >> >> XSTGInstrInfo.td:908:73: error: expected variable