Displaying 20 results from an estimated 1000 matches similar to: "OrcLazyJIT for windows"
2016 May 04
2
OrcLazyJIT for windows
Hi David,
This is really cool. I'd love to get this in-tree.
There are two ways we could go about this:
(1) Make the OrcArchitecture interface ABI-aware so that it can choose the
right resolver code,
or
(2) Replace the OrcArchitecture classes with OrcABI classes. I.e. We'd just
a rename OrcX86_64 -> Orc_X86_64_SysV (and rename I386 & AArch64 similarly)
, then we add your code as
2012 Oct 02
18
[PATCH 0/3] x86: adjust entry frame generation
This set of patches converts the way frames gets created from
using PUSHes/POPs to using MOVes, thus allowing (in certain
cases) to avoid saving/restoring part of the register set.
While the place where the (small) win from this comes from varies
between CPUs, the net effect is a 1 to 2% reduction on a
combined interruption entry and exit when the full state save
can be avoided.
1: use MOV
2015 Jul 13
5
[LLVMdev] Poor register allocations vs gcc
Hello,
I have an issue with the llvm optimizations. I need to create object codes.
the -ON PURPOSE poor && useless- code :
---------------------------------------------------
#include <stdio.h>
#include <stdlib.h>
int ci(int a){
return 23;
}
int flop(int a, char ** c){
a += 71;
int b = 0;
if (a == 56){
b = 69;
b += ci(a);
}
puts("ok");
return a +
2010 Sep 01
5
[LLVMdev] equivalent IR, different asm
The attached .ll files seem equivalent, but the resulting asm from 'opt-fail.ll' causes a crash to webkit.
I suspect the usage of registers is wrong, can someone take a look ?
$ llc opt-pass.ll -o -
.section __TEXT,__text,regular,pure_instructions
.globl __ZN7WebCore6kolos1ERiS0_PKNS_20RenderBoxModelObjectEPNS_10StyleImageE
.align 4, 0x90
2013 Aug 08
4
[LLVMdev] Address space extension
On Aug 7, 2013, at 7:23 PM, Michele Scandale <michele.scandale at gmail.com> wrote:
> On 08/08/2013 03:52 AM, Pete Cooper wrote:
>>> Why a backend should be responsible (meaning have knowledge) for a
>>> mapping between high level address spaces and low level address spaces?
>> Thats true. I’m thinking entirely from the persecutive of the backend
>> doing
2013 Aug 08
0
[LLVMdev] Address space extension
On 8 Aug 2013, at 04:23, Pete Cooper <peter_cooper at apple.com> wrote:
>
> On Aug 7, 2013, at 7:23 PM, Michele Scandale <michele.scandale at gmail.com> wrote:
>
>> On 08/08/2013 03:52 AM, Pete Cooper wrote:
>>
>> From here I understand that in the IR there are addrspace(N) where N=0,1,2,3,... according to the target independent mapping done by the
2010 Sep 01
0
[LLVMdev] equivalent IR, different asm
On Sep 1, 2010, at 6:25 AM, Argyrios Kyrtzidis wrote:
> The attached .ll files seem equivalent, but the resulting asm from 'opt-fail.ll' causes a crash to webkit.
> I suspect the usage of registers is wrong, can someone take a look ?
The difference is that there is a shift right after the multiply, before the divide. In IR, the difference is:
%5 = mul nsw i32 %4, %tmp1
2019 Feb 05
2
clang emits calls to consexpr function.
Hi Devs,
consider below testcase
$cat test.cpp
constexpr int product()
{
return 10*20;
}
int main()
{
const int x = product();
return 0;
}
$./clang test.cpp -std=c++11 -S
$./clang -v
clang version 9.0.0
Target: x86_64-unknown-linux-gnu
$cat test.s
main:
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq
2012 Mar 02
3
[LLVMdev] how to annotate assembler
Hi,
In GCC there is one useful option -dp (or -dP for more verbose output)
to annotate assembler with instruction patterns, that was used when
assembler was generated. For example:
double
test(long long s)
{
return s;
}
gcc -S -dp -O0 test.c
test:
.LFB0:
.cfi_startproc
pushq %rbp # 18 *pushdi2_rex64/1 [length = 1]
.cfi_def_cfa_offset 16
movq %rsp, %rbp # 19 *movdi_1_rex64/2
2016 Jun 30
4
Help required regarding IPRA and Local Function optimization
Hello Mentors,
I am currently finding bug in Local Function related optimization due to
which runtime failures are observed in some test cases, as those test cases
are containing very large function with recursion and object oriented code
so I am not able to find a pattern which is causing failure. So I tried
following simple case to understand expected behavior from this
optimization.
Consider
2013 Aug 08
2
[LLVMdev] Address space extension
On 08/08/2013 11:04 AM, David Chisnall wrote:
> What happens when I link together two IR modules from different front ends that have different language-specific address spaces?
I agree with Micah: if during the linking two IR modules there are
incoherences (e.g. in module1 2 -> 1 and in module2 2 -> 3) then the
modules are incompatible and the link process should fail.
> I would be
2017 Apr 05
2
Deopt operand bundle behavior
Hi!
We have started to use deopt operand bundle to make our native stacktrace deoptimizable and garbage collectable. We stumbled upon an issue and we don't know if it is really an issue on our side or really a problem within LLVM.
For example, for this input:
declare { i8*, i8* } @getCode()
define void @testFunc() {
entry:
%0 = call { i8*, i8* } @getCode()
%1 = extractvalue { i8*, i8* }
2017 Aug 24
1
Invalid Signature of orc::RTDyldObjectLinkingLayer::NotifyLoadedFtor
Hi all, hi Lang
It's a little late to report issues for release_50, but I just found
that thing while porting my JitFromScratch examples to 5.0.
This is a really nifty detail, but (if I'm not mistaken) the function
signature of RTDyldObjectLinkingLayer::NotifyLoadedFtor is incorrect:
$ grep -h -r -A 1 "using NotifyLoadedFtor"
2012 May 24
4
[LLVMdev] use AVX automatically if present
I wonder why AVX is not used automatically if available at the host
machine. In contrast to that, SSE41 instructions (like pmulld) are
automatically used if the host machine supports SSE41.
E.g.
$ cat avx.ll
define void @_fun1(<8 x float>*, <8 x float>*) {
_L1:
%x = load <8 x float>* %0
%y = load <8 x float>* %1
%z = fadd <8 x float> %x, %y
store
2014 May 11
2
[LLVMdev] [cfe-dev] Code generation for noexcept functions
On Sun, May 11, 2014 at 8:19 AM, Stephan Tolksdorf <st at quanttec.com> wrote:
> Hi,
>
> When clang/LLVM can't prove that a noexcept function only contains
> non-throwing code, it seems to insert an explicit exception handler that
> calls std::terminate. Why doesn't clang leave it to the eh personality
> function to call std::terminate when an exception is thrown
2015 Jul 13
2
[LLVMdev] Poor register allocations vs gcc
<br />Hello, <br />Ecx is a problem because you have to xor it. Which is avoided in the gcc compilation. Fomit-pointer-frame helps.<br /><br />Now llvm is one instruction from gcc. If ecx was not used, it would be as fast.<br />-- <br />Sent from Yandex.Mail for mobile<br /><br />20:03, 13 July 2015, Matthias Braun <mbraun@apple.com>:<br
2012 Mar 02
0
[LLVMdev] how to annotate assembler
On 02.03.2012, at 09:20, Konstantin Vladimirov wrote:
> Hi,
>
> In GCC there is one useful option -dp (or -dP for more verbose output)
> to annotate assembler with instruction patterns, that was used when
> assembler was generated. For example:
The internal "-mllvm -show-mc-inst" option is probably as close as you can get.
$ clang -S -O0 test.c -mllvm -show-mc-inst -o
2018 Sep 14
2
Function calls keep increasing the stack usage
Sorry I missed that important detail. The relevant part of the command line
is:
-cc1 -S -triple i386-pc-win32
I don't expect it matters if it's for Windows or Linux in this case.
On Fri, Sep 14, 2018 at 9:16 PM David Blaikie <dblaikie at gmail.com> wrote:
> Can't say I've observed that behavior (though I'm just building from
> top-of-tree rather than 6.0,
2011 Feb 21
2
[LLVMdev] Passing structures as pointers, MSVC x64 style
The MS x64 ABI calling convention (http://msdn.microsoft.com/en-us/library/ms235286(VS.80).aspx) says:
Any argument that doesn’t fit in 8 bytes, or is not 1, 2, 4, or 8 bytes, must be passed by reference.
Clang isn't doing that for us when passing our triple, x86_64-pc-win32-macho.
Here's a simple example program:
struct Guid {
unsigned int Data1;
unsigned
2011 Jan 02
2
[LLVMdev] X86 -tailcallopt and C calling conversion
Happy 2011, everybody!
It seems -tailcallopt prevents tailcall optimization when both caller
and callee have ccc,
even when it is optimized without an option -tailcallopt.
Is it intended or misoptimized?
In X86ISelLowering.cpp:X86TargetLowering::IsEligibleForTailCallOptimization():
if (GuaranteedTailCallOpt) {
if (IsTailCallConvention(CalleeCC) && CCMatch)
return true;