similar to: Reasoning about known bits of the absolute value of a signed integer

Hello, This simple patch fixes PR9112: Index: lib/Analysis/ValueTracking.cpp =================================================================== --- lib/Analysis/ValueTracking.cpp (revision 125281) +++ lib/Analysis/ValueTracking.cpp (working copy) @@ -593,6 +593,8 @@ // Otherwise take the unions of the known bit sets of the operands, // taking conservative care to avoid

Hi all, Hi Eli, No, that appears to be something unrelated. I'm currently using revision 75246, while that patch only seems to apply to some later revision. Anyway, I actually located the real bug. Right at the end of InstCombiner::SimplifyDemandedUseBits, there's this piece of code: // If the client is only demanding bits that we know, return the known // constant. if

On Thu, Jul 30, 2009 at 5:57 AM, Nicolas Capens<nicolas at capens.net> wrote: > No, that appears to be something unrelated. I'm currently using revision > 75246, while that patch only seems to apply to some later revision. I don't see the connection... anyway, I can't easily help you with an old revision. > Anyway, I actually located the real bug. Right at the end of

Can someone explain what this function is supposed to do? I've looked at PowerPC, Sparc, etc.. and can't really figure out what I should be doing here. Thanks, Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. 4555 Great America Pkwy, Santa Clara, CA. 95054 P: 408-572-6219 F: 408-572-6596 -------------- next part

On Wed, Jul 29, 2009 at 3:45 AM, Nicolas Capens<nicolas at capens.net> wrote: > So could anyone who knows the ins and outs of this code have a look at how > to make it handle vectors correctly? Or if that’s not an option right now, > please revert the broken optimizations. Note that there might be more things > affected than visitAnd, visitOr and vistXor, I’ve only been able to

Hi All, I found a regression which triggers the asserts: "Binary operator types must match!" and "Op types should be identical!". It's happening with a piece of vector code, and the asserts happen because a logic operation is attempted between a vector and a scalar (which is not present in the original code, but created by InstCombine). It's caused by revision

Hi all, I'm instrumenting IR by replacing loads and stores by calls to a library, which I have compiled to bitcode such that inlining can take place. My problem is: If I could retain the alignment information on the load/store, this would open many optimization opportunities after inlining. Unfortunately, I don't know how. After thinking about it, and trying different things, I now

I checked the capabilities. I do not know why the guest is only for vbox. <guest> <os_type>hvm</os_type> <arch name='i686'> <wordsize>32</wordsize> <domain type='vbox'> </domain> </arch> </guest> I want it run qemu-kvm. and when i run virsh define /etc/libvirt/qemu/demo.xml. It shows error:

On 06/11/2018 02:33 PM, Friedman, Eli via llvm-dev wrote: > On 6/11/2018 10:06 AM, jingu at codeplay.com via llvm-dev wrote: >> Hello All, >> >> I have met one may-alias case from llvm's alias analysis. The code >> snippet is as following: >> >> char buf[4]; >> >> void test (int idx) { >> char *a = &buf[3 - idx]; >> char *b =

Hi Clemens, > I'm instrumenting IR by replacing loads and stores by calls to a library, which > I have compiled to bitcode such that inlining can take place. My problem is: If > I could retain the alignment information on the load/store, this would open many > optimization opportunities after inlining. Unfortunately, I don't know how. > > After thinking about it, and

Hello Community, I successfully installed and run xen (xm list and xm info can output appropriately). However, while I was installing domU image by using virt-install -p at domU OS. I encountered an error information" Host does not support virtualization type ''xen'' ". I built xen from source. Some of my friends have the same issue, but if they use pre-build xen, the

Hi Duncan, thanks for your comments. >> First, consider this function: >> #include <stdint.h> >> uint64_t foo(uint64_t *bar) { >> *bar = 42; >> return (uint64_t)bar & 3; >> } >> >> Which is compiled to >> define i64 @foo(i64* %bar) nounwind uwtable ssp { >> store i64 42, i64* %bar, align 8 >>

In tracking down an alignment bug, I think I found a problem in ComputeMaskedBits. But I am not very well versed in this area of LLVM and need some more eyes. This is in the 2.3 release, though it looks like the relevant pieces operate the same way in trunk. I have the following add recurrence: %r849 = select i1 %r848, i64 0, i64 %r847 ; <i64> [#uses=10] %r862 = shl i64 %r849, 3 ;

Hello All, I have met one may-alias case from llvm's alias analysis. The code snippet is as following: char buf[4]; void test (int idx) { char *a = &buf[3 - idx]; char *b = &buf[idx]; *a = 1; *b = 2; } I can see below output from alias set tracker for above code snippet. Alias sets for function 'test': Alias Set Tracker: 1 alias sets for 2 pointer values.  

On Friday 18 July 2008 00:36, Nick Lewycky wrote: > David Greene wrote: > > Is my analysis correct? If so, is the PHI code the culprit (for not > > returning the min of the KnownZero bits) or is the Shl code the culprit > > (for not paying attention to the Mask passed in (it right shifts it)? > > I think your analysis is correct, and that Shl -- and many of the other

David Greene wrote: > Is my analysis correct? If so, is the PHI code the culprit (for not returning > the min of the KnownZero bits) or is the Shl code the culprit (for not paying > attention to the Mask passed in (it right shifts it)? I think your analysis is correct, and that Shl -- and many of the other operations (AShr, LShr, SExt, Add?, Call?) -- should be modified to always

Hi, Please let me know in case I am posting my question to the wrong forum. I apologize if that is the case! Here is my question: We run CentOS 6.3 on a server with dual Xeon CPU's. Our "dual blade" server uses this motherboard: http://www.supermicro.com/products/motherboard/Xeon/C600/X9DRT-HF.cfm We have two of these CPUs installed and working: Intel(R) Xeon(R) CPU E5-2620 0 @

Hi Clemens, > thanks for your comments. > >>> First, consider this function: >>> #include <stdint.h> >>> uint64_t foo(uint64_t *bar) { >>> *bar = 42; >>> return (uint64_t)bar & 3; >>> } >>> >>> Which is compiled to >>> define i64 @foo(i64* %bar) nounwind uwtable ssp {

On Tue, Jun 2, 2009 at 6:26 PM, robert muth<robert at muth.org> wrote: > This is my first patch submission. Hopefully, this is the proper the protocol. This is fine, although it's usually better to submit patches to llvm-commits. > Added mechanism to generate switch table in a data section > rather than having it interleaved with the code. > This is controlled by command

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