similar to: enable/disable features through clang

I'm trying to enable/disable a target feature through clang. Here is how my target looks like // Esencia subtarget features //===----------------------------------------------------------------------===// def FeatureMul : SubtargetFeature<"mul", "HasMul", "true", "Enable hardware multiplier">; def FeatureDiv

Hi, I have a data.frame that looks something like this. feature 5637 ? ? ? ? ? ? ? ?1321N1 feature1 -0.568750616 -0.934748758 feature2 -0.913080902 -0.941455172 feature3 0.442477294 -0.257921866 I want to change it to look like this. feature ? ? ?cell.line ? ? value feature1 5637 -0.568750616 feature2 5637 -0.913080902 feature3 5637 0.442477294 feature1 1321N1

Dear all, I have a data frame, which looks like this: Subject | Block | Trial | Feature1 | Feature2 .... 1 | 1 | 1 | ... | ... 1 | 1 | 2 | ... | ... 1 | 2 | 1 | ... | ... 1 | 2 | 2 | ... | ... 1 | 3 | 1 | ... | ... ...| ...| ...| ... | ... Can I remove the "Trial" column by averaging all the rows and without using a "for loop"? At the end my data frame should look like

My target has an instruction that adds up all elements in the vector and stores the result in a register. I'm trying to implement it in my compiler but I'm not sure even where to start. I did look at other targets, but they don't seem to have anything like it ( I could be wrong. My experience with LLVM is limited, so if I missed it, I'd appreciate if someone could point it out ).

Hi Rail, Below 2 revisions might be of your interest which Detect SAD patterns and emit psadbw instructions on X86.: http://reviews.llvm.org/D14840 http://reviews.llvm.org/D14897 Intrinsics related to absdiff revisons : http://reviews.llvm.org/D10867 http://reviews.llvm.org/D11678 Hope this helps. Regards, Suyog On Sat, May 28, 2016 at 4:20 AM, Rail Shafigulin via llvm-dev < llvm-dev at

Hi, I'd like to propose extending the supported syntax for AssemblerPredicates to allow sets of SubtargetFeatures to be listed, but where only one in the list has to be enabled for the predicate to be true. The condition string which forms a AssemblerPredicate already allows multiple features to be defined, separated by commas, and this means all of these features must be present. For

On Thu, Jan 28, 2016 at 8:34 PM, Dylan McKay <dylanmckay34 at gmail.com> wrote: > Try visualising the DAG like this. > > ``` > ---- GPR:$rA > / > set GPR:$rd ---- add > \ > ---- GPR:$rB > ``` > > Each instruction forms a DAG with its operands being subnodes. > >

> On Feb 1, 2016, at 16:53, Rail Shafigulin <rail at esenciatech.com> wrote: > > > > On Fri, Jan 29, 2016 at 10:03 PM, Matt Arsenault <arsenm2 at gmail.com <mailto:arsenm2 at gmail.com>> wrote: > > > On Jan 29, 2016, at 13:25, Rail Shafigulin via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: > > >

> why in order to add this particular instruction (sum elements in a vector) I need to add an insrinsic? Adding intrinsic is not the only way, it is one of the way and user WILL-NOT be required to invoke It specifically. Currently LLVM does not have any instruction to directly represent “sum of elements in a vector” and generate your particular instruction.However, you can do it without

This would be really cool. We have several instructions that perform horizontal vector operations, and have to use built-ins to select them as there is no easy way of expressing them in a TD file. Some like SUM for a ‘v4i32’ are easy enough to express with a pattern fragment, SUM ‘v8i16’ takes TableGen a long time to compute, but SUM ‘v16i8’ resulted in TableGen disappearing into itself for

I've created an intrinsic from my target, but I can't figure out how I can run it from a C code. Most of the targets have a GCCBuiltin and it looks like it is the way to execute an intrinsic from C code. However in my case there is no actual GCC built in. Any help on this is really appreciated. -- Rail Shafigulin Software Engineer Esencia Technologies -------------- next part

Hi Shahid. Do you mind providing a concrete example of X86 code where an intrinsic was added (preferrable with filenames and line numbers)? I'm having difficulty tracking down the steps you provided. Any help is appreciated. On Mon, Apr 4, 2016 at 9:02 PM, Shahid, Asghar-ahmad < Asghar-ahmad.Shahid at amd.com> wrote: > Hi Rail, > > > > We had done this for generation

Hi Rail, We used a very simple pattern expansion (actually, not a pattern fragment). For example, for AND, ADD (horizontal sum), OR and XOR of 4 elements we use something like the following TableGen structure: class HORIZ_Op4<SDNode opc, RegisterClass regVT, ValueType rt, ValueType vt, string asmstr> : SHAVE_Instr<(outs regVT:$dst), (ins VRF128:$src),

My question is: How do I make clang to generate assembly with vector instruction for my target? The back story is: I've added a few vector instructions to my target and confirmed that they are used by running my code on the test below and using a following command: opt i.esencia.ll -S -march=esencia -mcpu=esencia -loop-vectorize | llc -mcpu=esencia -o i.esencia.s target datalayout =

On Fri, Mar 18, 2016 at 2:03 PM, Rail Shafigulin <rail at esenciatech.com> wrote: > On Fri, Mar 18, 2016 at 1:53 PM, Mehdi Amini <mehdi.amini at apple.com> > wrote: > >> >> On Mar 18, 2016, at 1:47 PM, Rail Shafigulin <rail at esenciatech.com> >> wrote: >> >> Yes this IR does not build or shuffle any vector. Try to write a function

> > Here is how I started with SelectionDAG: > > - small IR (bugpoint can help) > Did you mean a break poing? - the magic flag: -debug > - read the output of SelectionDAG debugging (especially with cycles) > - matching the log to source code > What log are you talking about? > - single stepping in a debugger sometimes. > > > -- > Mehdi > > -- Rail

I'm starting to think we should directly implement horizontal operations on vector types. My suspicion is that coming up with a nice model for this would help us a lot with things like: - Idiom recognition of reduction patterns that use horizontal arithmetic - Ability to use horizontal operations in SLPVectorizer - Significantly easier cost modeling of vectorizing loops with reductions in

On Fri, Jan 29, 2016 at 11:39 AM, Rail Shafigulin <rail at esenciatech.com> wrote: > > > On Thu, Jan 28, 2016 at 8:34 PM, Dylan McKay <dylanmckay34 at gmail.com> > wrote: > >> Try visualising the DAG like this. >> >> ``` >> ---- GPR:$rA >> / >> set GPR:$rd ---- add >>

On 4/28/2016 2:11 PM, Rail Shafigulin wrote: > > On Thu, Apr 28, 2016 at 6:13 AM, Krzysztof Parzyszek > <kparzysz at codeaurora.org <mailto:kparzysz at codeaurora.org>> wrote: > > > IIRC, > > What is IIRC? If I remember correctly... -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

There are uses of R0 all over the place, even though R0 is not marked as live-in to any of the blocks that use it. For example: BB#45: derived from LLVM BB %sw.bb54 Predecessors according to CFG: BB#43 BB#44 DBG_VALUE %vreg287, %noreg, !"base" %vreg203<def> = LWZ <fi#5>, 0; mem:LD4[%args] GPR:%vreg203 %vreg204<def> = ADDI %vreg203, 3;