similar to: Link using a linker script

search for VAStart. Cheers, Rafael On 20 April 2016 at 14:18, Sky Flyer <skylake007 at gmail.com> wrote: > Hi Rafael, > > Thanks a lot. > For example the start entry for me is 0x11000 by default which I don't know > where it come from! I thought there should be a default thing that sets this > entry address. > > On Wed, Apr 20, 2016 at 8:05 PM, Rafael Espíndola

For example something like STARTUP ( http://wiki.osdev.org/Linker_Scripts#STARTUP) is not accepted by the LLVM LLD. :-/ On Wed, Apr 20, 2016 at 9:08 PM, Sky Flyer <skylake007 at gmail.com> wrote: > Yeah I found it, that's nice. Thanks a milion. > Could you please tell me how can I specify my bootstrap (startup code) in > the linking process? > > > On Wed, Apr 20, 2016

There is no default linker script. Cheers, Rafael On 20 April 2016 at 11:23, Sky Flyer via llvm-dev <llvm-dev at lists.llvm.org> wrote: > for instance, where is the internal default linker script located? How can I > change the default values, for example the star address... > > On Wed, Apr 20, 2016 at 5:17 PM, Sky Flyer <skylake007 at gmail.com> wrote: >> >>

Hi, That's what the DecoderMethod is for. Similarly ParserMatchClass for the asm parser and PrintMethod for the asm printer: def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; } def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm), (ops (i32 14), (i32 zero_reg))> { let PrintMethod = "printPredicateOperand";

Hi ES, From what I understand instruction parsing is divided into two parts: - Parsing an operand list (XXXAsmParser::ParseInstruction) - Turning the operand list into an actual instruction (XXXAsmParser::MatchAndEmitInstruction) The second part does the validation (e.g. how many operands, what kind, etc) while the first part only does the parsing. That's why I think in the first part

Hello James, that was also what I've planned to do but just wasn't sure. Thanks for that. On Mon, Dec 14, 2015 at 11:52 AM, James Molloy <james at jamesmolloy.co.uk> wrote: > Hi, > > You can't nest operands like that - it must be a flattened list. So: > > def *Xpred* : PredicateOperand<OtherVT, (ops *i32imm, i32imm*, i32imm), > (ops (i32 14), (i32

Hi all, in most of the architectures, assembly operands are comma-separated. I would like to parse an assembly code that is space-separated and I am having a bit of problem. In *ParseInstruction* function, I don't know what is the easiest way to figure out how many operands a mnemonic expected to have. In comma-separated assembly code, it just consuming commas (while

Hello all, I don't find anything helping me understand the llvm bang operator. In the llvm TableGen language reference, it only says: 'TableGen also has “bang operators” which have a wide variety of meanings: *'* I would be very thankful if someone can explain it to me. e.g. what does "!strconcat" or "!if" mean? Cheers ES -------------- next part --------------

On Thu, Jul 23, 2015 at 9:53 AM, Sky Flyer <skylake007 at googlemail.com> wrote: > Hello all, > > I don't find anything helping me understand the llvm bang operator. In the > llvm TableGen language reference, it only says: > > 'TableGen also has “bang operators” which have a wide variety of meanings:' > > I would be very thankful if someone can explain it

Thanks a lot Tim. I am getting an error which says: "LLVM ERROR: unable to write nop sequence of 0 bytes" Is there any way that I can print out the Obj code (I mean bitstream representation of the assembly code which is going to be placed in the ELF file), before making any ELF file? Cheers, ES On Tue, Oct 13, 2015 at 3:02 PM, Tim Northover <t.p.northover at gmail.com> wrote:

On 11/6/2015 11:35 AM, Sky Flyer via llvm-dev wrote: > Guys, I stuck at this point. Could you please give me a hint how to > solve this problem without touching the LLVM backbone?! > Why LLVM doesn't let me define an instruction consisting of an operator > with no operand? Could you try it without the pattern? I.e. just this: class TestInst<string opc, string asmstr,

Hi all, I have implemented AsmParser, CodeEmitter, and ELF object writing. AsmParser and CodeEmitter are tested and working fine, but I would like to see ELF objects build out of a parsed asm file. Is that possible? I tried this commands, but it didn't work corrctly: *llvm-mc -filetype=obj -arch=test file.s -o=a.o* and I think after an obj file is built, I should use this command but I am

Dear all, in my TestRegisterInfo.td file, I defined a register like this: class TestReg<bits<6> enc, string name> : Register<name> { let HWEncoding{5-0} = enc; let Namespace = "TEST"; } def D0 : TestReg<0x01, "d0">, DwarfRegNum<[1]>; but when I compile, the result I have in TestGenAsmMatcher.inc is this: case 'd': // 7

Hi all, I am trying to implement an instruction with no operand for example "clr" in TableGen. ----------------------------------------- e.g. *InstrInfo.td:* class TestInst<string opc, string asmstr, dag oops, dag iops, list<dag> pattern> : Instruction { ... } def int_no_operand : Intrinsic<[]>; class ALU<string opc> : TestInst<opc,

Hi Krzystof, regarding your first solution (creating separate instruction), is it possible to somehow have cascading defm? for example, let's suppose aaa is a 3-bit condition a, and bb is a 2-bit condition b, all in one instruction, instead of having one multiclass with 2^5 conditions, is it possible to write 2^3 "a" conditions, and 2^2 "b" conditions, and the rest taken

Hi Tom, Thanks. It should be always ABC. What should be the iops? just (ins i8imm:$val)? what would be the placeholder for a constant string in "ins"? On Thu, Nov 5, 2015 at 4:33 PM, Tom Stellard <tom at stellard.net> wrote: > On Thu, Nov 05, 2015 at 03:20:45PM +0100, Sky Flyer via llvm-dev wrote: > > Hello all, > > > > how can one can describe a constant

Thanks Meador, The confusion point for me is that, does ! as an operator (bang operator) add any meaning to the strconcat? On Thu, Jul 23, 2015 at 5:25 PM, Meador Inge <meadori at gmail.com> wrote: > On Thu, Jul 23, 2015 at 9:53 AM, Sky Flyer <skylake007 at googlemail.com> > wrote: > > > Hello all, > > > > I don't find anything helping me understand

Dear all, I am trying to write an AsmParser and a CodeEmitter for simple ADD instruction. Here is what I have in the TestGenInstrInfo.td: *extern const MCInstrDesc TestInsts[] = {...{ 23, 3, 1, 0, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo13, 0, nullptr }, // Inst #23 = ADD8_rr...}* I parse the instruction successfully but I am not sure what I did wrong that the Size (as you can see in

Thank you :) If you mean this field, it looks everything is ok: field bits<16> Inst = { 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, Dr{2}, Dr{1}, Dr{0}, At{0}, 0, 0 }; Is possible that the problem might be on the TestAsmParser.cpp side? On Thu, Sep 17, 2015 at 4:18 PM, Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 9/17/2015 9:04 AM, Krzysztof Parzyszek via llvm-dev

Hi all, what is exactly "zero_reg"? from ARMInstFromats.td: *def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm), (ops (i32 14), (i32 zero_reg))> {...}* I thought zero_reg can be replace by a random name like (alu_stat_reg for alu state register) but when I compiled it, I figure out that zero_reg is a predefined variable. Can someone please give me more information about