similar to: Experimental 6502 backend; memory operand folding problem

So I've been designing an experimental 6502 backend for LLVM. Link: <https://github.com/beholdnec/llvm-m6502> The 6502 only has a few registers, one accumulator and two indexes, none of which are large enough to hold an absolute pointer. Because of this, the backend really tests the power of LLVM's register allocator (RA). I've made a change to the RA that might be of interest

I suppose that once you've got a 6502 working, adding support for a 4510 shouldn't be too difficult.... (http://c65gs.blogspot.com.au/) On Fri, Jul 4, 2014 at 10:38 AM, Bruce Hoult <bruce at hoult.org> wrote: > On Fri, Jul 4, 2014 at 12:02 PM, Edwin Amsler <edwinguy at gmail.com> wrote: > >> Well, the stack pointer be a single byte, so pushing things on there

Well, the stack pointer be a single byte, so pushing things on there doesn't work terribly well. Assuming I pass by reference, that's 128 values absolutely total before it wraps around and silently clobbers itself. It means single byte values will be incredibly inefficient... Tricky stuff. I'm lucky on the C64 since it's rare to exit back to the kernel with machine language apps

Not only do FPGAs not support recursion, we don’t even support calls! All user code must be inlined into one kernel/component, which is then used to create HDL for the FPGA. Mark From: Bruce Hoult <brucehoult at sifive.com> Sent: December 17, 2018 9:28 AM To: Mendell, Mark P <mark.p.mendell at intel.com> Cc: jjones at prc-hsv.com; LLVM Developers Mailing List <llvm-dev at

I never thought I’d see the day when someone proposed treating the 6502 like a GPU… —escha > On Feb 12, 2016, at 6:30 AM, Bruce Hoult via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > I think it would be sufficient to pick 8 or 16 pairs of zero page locations as the "registers". Who needs 128 registers, unless you're also doing inter-procedural register

On 2/12/2016 7:23 AM, Bruce Hoult via llvm-dev wrote: > I haven't seen what you are doing, but if I was writing a back end for > the 6502, I'd lie to LLVM and describe RAM page 0 as being the real > registers, and A, X and Y as being special purpose registers used for > temporaries. How did you get the "(z), x" and "(z, y)" addressing modes to work with

hi, I use the oh323 driver to answer H323 calls. The connection is set up normally. In my extensions.conf file I use: exten => s,1,Answer exten => s,2,Playback(demo-instruct) exten => s,3,Hangup So that when a call is answered i get: *CLI> -- Executing Answer("H323/ip$10.0.3.23:32782/6502", "") in new stack -- Executing

Inspired by Jason Turner's talk at CppCon 2016: Jason Turner “Rich Code for Tiny Computers: A Simple Commodore 64 Game in C++17” I got interested in writing a Zilog Z80 backend for LLVM. Jason actually did no such thing, but instead wrote a x86-to-6502 translator (reassembler he calls it) https://github.com/lefticus/x86-to-6502 So I'm now trying to bootstrap this project. Goal: - be

i am not able to join the domain using ads and target ip ( net ads join ?S <domain controller ip> ?U <username> ). I am getting below error. *net ads join -S 172.17.100.97 -U administrator* *Enter administrator's password:* *kinit succeeded but ads_sasl_spnego_krb5_bind failed: Server not found in Kerberos database* *Failed to join domain: failed to connect to AD: Server not found

I currently have an AGI that calls the Festival text2wave app to write a wav file that my dialplan plays into a call with the Background() command. But the voice sounds terrible: like SAM, the 1980s 6502 voice synthesizer. I tried to slow it down by calling (text2wav -eval "(Parameter.set 'Duration_Stretch 1.4)" -scale 2.0 [...]), but it still sounds like it's talking while

Hello, Here is one question regarding the LLVM TableGen: Which file in the llvm/lib/Target/X86 folder describes how the bits in the EFLAGS register are modified by the x86 instructions? For example, in the "X86InstrInfo.td" file, lines 2134-2135, it says: let SchedRW = [WriteALU], Defs = [EFLAGS], Uses = [EFLAGS] in { def CLC : I<0xF8, RawFrm, (outs), (ins), "clc",

Hi, poma wrote: > Hardly anyone reads manuals these days. There are manuals ? El Torito just specifies how to direct the BIOS to the boot image, and what the boot image can learn from the BIOS about its origin. Possibly this silently builds on MBR specs. But about those i can only find wikipedia rumors: "the CPU is in real mode and the general-purpose and segment registers are

I've mentioned my sneaky plans to target the MOS6502 here before. The big issue I think is that a lot of instructions don't really have a choice for output register. It all just goes into the accumulator, X index, or Y index based on the specific instruction. So, my question is, when I'm defining my ins, outs and registers for these instructions, is it going to be a problem that

Hi, I'm doing a backend port and I'm having trouble with adds that have negative immediates. My architecture only has instructions for subtracting and adding 8bit immediate values (they will be zero-extended, thus unsigned). Bigger immediates have to be moved in a register first. The problem is: Expressions like "b - 1" result in "add nsw i32 %b, -1" in LLVM IR. They

July 15, 2019 1:16 PM, "Bruce Hoult" <brucehoult at sifive.com> wrote: > Take, for example, RISC-V. You have 32 registers that, in the base > fixed-length 32 bits long instruction set, are absolutely > interchangeable with each other. No instructions use implicit source > or destination registers, any register can be used for anything. There > is no fixed stack

Dear All, I am trying to custom lower 32-bit ISD::SHL and SHR in a backend for 6502 family CPUs. The particular subtarget has 16-bit registers at most, so a 32-bit result is not legal. Normally, if you mark this as "Legal" or "Expand", then it will expand the node into a more nodes as follows in an example: shl i32 %a , 2 => high_sdvalue = (or (shr %b, 14), (shl %c, 2) )

On 27 Jun 2015, at 16:13, escha <escha at apple.com> wrote: > >> >> Hi, >> >> I recently started helping with the LLVM AVR backend [1]. The AVR is an 8 bit core with pointer type i16. That makes pointers illegal in the SelectionDAG. As far as I understand it, it is the backends job to legalize these nodes by using the ReplaceNodeResults/LowerOperation callbacks.

Hello, My package has passed all the R CMD CHECK steps except one. There is an object which I placed in a sysdata.rda file (located in the 'R' directory of the source package). Even though users have no need to access this object, which is a character vector of parameters fed to Fortran code, R CMD CHECK produces a warning that it needs documentation. So I made an .Rd file for it. However,

I had a similar problem with a backend for the 68HC12 family which also has no barrel shifter. Some 68HC12 CPUs support shift for just one of the 16-bit registers and only support rotation on the 2 8-bit subregs of that 16-bit register. That means the only practical solution for 32-bit shifts is to lower to a libcall but my situation for 16-bit shifts sounds similar to yours for 32-bit shifts. I

I believe that what I'm trying to do with Clang is fairly simple; the final goal, however, might be a little harder. Knowing myself, there are chances I'll never go through with this project (like Mikael who posted earlier, I'm nothing but an enthusiastic student with lots of time on my hands), but it feels cool enough to me to announce my idea. Besides, I'll probably need help