similar to: [GVN] same sequence of instructions in if and else branch

Displaying 20 results from an estimated 7000 matches similar to: "[GVN] same sequence of instructions in if and else branch"

2016 Feb 09
2
[GVN] same sequence of instructions in if and else branch
There is a phi-node "%phi = phi i64 [%cast1, %if], [%cast2, %else]" in the common successor. The actual control flow is a bit more complex, but there is a common successor block, and %cast1 and %cast2 are the two values that the phi node in the common successor takes. Does the existence of the phi node affect optimization? Thanks, Taewook From: <mats.o.petersson at
2016 Feb 09
2
[GVN] same sequence of instructions in if and else branch
and by "right thing" i mean it can hoist if you want and it can prove it will not extend the live range. Note that VBE (very busy expressions) is a code size optimization only. It does not save time. On Tue, Feb 9, 2016 at 12:26 PM, Daniel Berlin <dberlin at dberlin.org> wrote: > This GVN does not do that, this is correct. It is a very simple GVN. All > phi nodes are
2018 Apr 18
1
[RFC] Making GVN able to visit the same block more than once
Introduction ============ I'm currently in the middle of what initially looked to be a simple change in GVN but is turning out to have unexpected consequences that are turning out to be quite difficult to resolve, so I thought I'd send out an RFC to make sure that I'm not barking up the wrong tree with how I'm trying to do this. Motivation and current behaviour
2016 Oct 06
2
LoopVectorizer -- generating bad and unhandled shufflevector sequence
Hi, I have experimented with enabling the LoopVectorizer for SystemZ. I have come across a loop which, when vectorized, seems to have been poorly generated. In short, there seems to be a completely unnecessary sequence of shufflevector instructions, that doesn't get optimized away anywhere. In other words, there is a shuffling so that leads back to the original vector: [0 1 2 3
2003 Jun 03
1
[LLVMdev] Problem with `as'
Hi, I am trying to assemble a preety simple program, but the assembler is giving parse errors: =========================== %.LC0 = internal constant [17 x sbyte] c"Hello World %d \0A\00" %.LC1 = internal constant [17 x sbyte] c"yyyyyyyyyyyyyyy\0a\00" declare int "puts"(sbyte*) int "main"() { %cast1 = getelementptr [17 x sbyte]* %.LC0, long 0, long 0
2017 Apr 05
2
[NewGVN] Plan for GVNPRE?
Hi Daniel, Got it. If that's the case, can I implement it under the guidance of your insights/prototype? I think I can spend more time on implementation. Thanks, Taewook ________________________________ From: Daniel Berlin <dberlin at dberlin.org> Sent: Tuesday, April 4, 2017 9:41:30 PM To: Taewook Oh Cc: llvm-dev at lists.llvm.org Subject: Re: [llvm-dev] [NewGVN] Plan for GVNPRE? Of
2017 Apr 05
2
[NewGVN] Plan for GVNPRE?
Hi Daniel, Thank you for your detailed reply, and thank you for working on GVNPRE. I’d more than happy to test/evaluate it with our benchmark once it is ready. Please let me know if you need any help. Thanks, Taewook From: Daniel Berlin <dberlin at dberlin.org> Date: Tuesday, April 4, 2017 at 6:13 PM To: Taewook Oh <twoh at fb.com> Cc: "llvm-dev at lists.llvm.org"
2017 Apr 04
2
[NewGVN] Plan for GVNPRE?
Hello, In some of our internal benchmarks, I observe that LLVM performs worse than GCC because LLVM fails to perform PRE when GCC can. I hope this problem goes away when NewGVN equipped with PRE, and wonder if anyone has an idea about the status of PRE on top of NewGVN. Thanks! Best, Taewook -------------- next part -------------- An HTML attachment was scrubbed... URL:
2013 Oct 21
5
[LLVMdev] First attempt at recognizing pointer reduction
Hi Nadav, Arnold, I managed to find some time to work on the pointer reduction, and I got a patch that can make "canVectorize()" pass. Basically what I do is to teach AddReductionVar() about pointers, saying they don't really have an exit instructions, and that (maybe) the final store is a good candidate (is it?). This makes it recognize the writes and reads, but then
2013 Aug 22
2
[LLVMdev] scev questions
Hi, I'm trying to get the following loop to vectorize (simple reduction): unsigned int sum2(unsigned int *a, int len){ unsigned int s = 0; for (int i = 0; i < len; i += 4) s += *a++; return s; } The loop fails to vectorize because SCEV could not compute the loop exit count. It appears SCEV cannot handle the non-unit increment of the loop counter. Is this a known limitation of
2013 Sep 11
0
[LLVMdev] removing unnecessary ZEXT
Hi Andrew, Thank you for the suggestion. I've looked at CodeGenPrepare.cpp and MoveExtToFormExtLoad() is never run. I also notice that the ARM target produces the same additional register usage (copy) and zero extending (of the copy). (See the usage of r3 &r5 and also r12 & r4 in attached file arm-strcspn.s, my understanding is that 'ldrb' is zero extending.) Here is a
2016 Nov 16
3
[RFC] NewGVN
On 16 Nov 2016, at 19:03, Davide Italiano <davide at FreeBSD.org> wrote: > >>> >>> For our target, this is only sound if you can show that the pointer was >>> used to read all of the bytes that you are loading (we have byte-granularity >>> memory safety). Old GVN has no hooks for targets to specify whether this is >>> safe and so is
2015 Jan 23
2
[LLVMdev] question about enabling cfl-aa and collecting a57 numbers
Without the patch is also returns the wrong answer for all of these, it just doesn't cause LICM to promote because it returns PartialAlias (which is still wrong). We return may-alias instead, and now suddenly it's happy to promote them. The broken noalias results exist both before and after my patch: ===== Alias Analysis Evaluator Report ===== 521 Total Alias Queries Performed
2020 Jul 02
3
Redundant ptrtoint/inttoptr instructions
Hi all, We noticed a lot of unnecessary ptrtoint instructions that stand in way of some of our optimizations; the code pattern looks like this: bb1: %int1 = ptrtoint %struct.s* %ptr1 to i64 bb2: %int2 = ptrtoint %struct.s* %ptr2 to i64 %bb3: %phi.node = phi i64 [ %int1, %bb1 ], [%int2, %bb2 ] %ptr = inttoptr i64 %phi.node to %struct.s* In short, the pattern above arises due to: 1.
2007 Jan 06
2
[LLVMdev] More detailed example...
> How are you compiling this? I get the following sort of output: > > llvm-gcc incdec.cpp -o incdec I am currently using LLVM 1.8 -- I was basically holding off porting until LLVM 2.0 stabilises because I want to be able to move to 64 bit Intel and don't want to have to hit a moving target. > void %inc(int* %p) { > entry: > %tmp = volatile load int* %p
2015 Jan 24
2
[LLVMdev] question about enabling cfl-aa and collecting a57 numbers
No, i mean the actual store instruction looks like "store i16 %conv22, i16* getelementptr inbounds ([16 x i16]* @pA, i64 0, i64 12), align 2, !tbaa !1" Not that the pointer operand comes from a GEP, but it is a constantexpr, whose opcode is GEP. It sucks that there is such a complex thing to be handled as a store operand directly , but such is life ... CFL-AA *should* treat this
2016 Nov 17
3
[RFC] NewGVN
On 16 Nov 2016, at 21:56, Daniel Berlin <dberlin at dberlin.org> wrote: > > You keep talking about platforms, but llvm ir itself is not platform dependent. > Can you give a reference in the language reference that says that this is not legal? Nothing in the LangRef (apart from the note about non-integral pointers, which was added recently) makes any claim about the representation
2014 Jul 23
3
[LLVMdev] On semantics of add instruction - nsw,nuw flags
On Wed, Jul 23, 2014 at 4:06 PM, Rekha R <rekharamapai at nitc.ac.in> wrote: > Ok. Got it. > > If *add nsw* overflows, this results in undefined value. > But then *add* on same arguments results in well-defined value. > > Hence treating first one as redundant based on the second is acceptable. > But vice versa is not. > If they are in different code paths, sure.
2015 Jan 23
2
[LLVMdev] question about enabling cfl-aa and collecting a57 numbers
Works for me On Thu, Jan 22, 2015 at 8:27 PM, Daniel Berlin <dberlin at dberlin.org> wrote: > We should use graph edges, so we can do something better at set build time > :) > > > On Thu Jan 22 2015 at 5:20:46 PM George Burgess IV < > george.burgess.iv at gmail.com> wrote: > >> > Should we be added an edge from the inttoptr to all other pointer >>
2016 May 05
2
No remapping of clone instruction in CloneBasicBlock
Hi, Found CloneBasicBlock utility only does the cloning without any remapping. Consider below example: Input block: sw.epilog: ; preds = %sw.bb20, %sw.bb15, %sw.bb10, %sw.bb6, %sw.bb2, %sw.bb, %while.body, %if.end29 %no_final.1 = phi i32 [ %no_final.055, %while.body ], [ 1, %if.end29 ], [ %no_final.055, %sw.bb20 ], [ %no_final.055, %sw.bb15 ], [