similar to: Reducing DWARF emitter memory consumption

Thanks, I'll look into that. (Though earlier you told me that debug info for types could be extended while walking the IR, so I wouldn't have thought that would have worked.) Peter On Fri, Feb 05, 2016 at 03:52:19PM -0800, David Blaikie wrote: > Will look more closely soon - but I'd really try just writing out type > units to MC as soon as they're done. It should be

Pete Cooper and I have been looking at memory profiles of running llc on verify-uselistorder.lto.opt.bc (ld -save-temps dump just before CodeGen of building verify-uselistorder with -flto -g). I've attached leak-backend.patch, which we're using to make Intrustruments more accurate (instead of effectively leaking things onto BumpPtrAllocators, really leak them with malloc()). (I've

With just those four patches, memory usage went *up* slightly. Add in the 5th patch (which does #2 below), and we get an overall memory drop of 4%. The intermediate result of a memory increase makes sense. While the first four patches reduce the number of (and size of) `DIEValue` allocations, they increase the cost of the `SmallVector` overhead. 0005 (attached) squeezes the abbreviation data

On Fri, Feb 05, 2016 at 04:58:45PM -0800, Mehdi Amini wrote: > > > On Feb 5, 2016, at 3:17 PM, Peter Collingbourne via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > > Hi all, > > > > We have profiled [1] the memory usage in LLVM when LTO'ing Chromium, and > > we've found that one of the top consumers of memory is the DWARF emitter in

On Fri, Feb 5, 2016 at 5:51 PM Mehdi Amini via llvm-dev < llvm-dev at lists.llvm.org> wrote: > > > On Feb 5, 2016, at 5:40 PM, Peter Collingbourne <peter at pcc.me.uk> wrote: > > > > On Fri, Feb 05, 2016 at 04:58:45PM -0800, Mehdi Amini wrote: > >> > >>> On Feb 5, 2016, at 3:17 PM, Peter Collingbourne via llvm-dev < > llvm-dev at

On Fri, Feb 5, 2016 at 5:56 PM, Mehdi Amini via llvm-dev < llvm-dev at lists.llvm.org> wrote: > > On Feb 5, 2016, at 5:53 PM, Eric Christopher <echristo at gmail.com> wrote: > > > > On Fri, Feb 5, 2016 at 5:51 PM Mehdi Amini via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> >> > On Feb 5, 2016, at 5:40 PM, Peter Collingbourne

> On 2015 May 20, at 17:51, Duncan P. N. Exon Smith <dexonsmith at apple.com> wrote: > > >> On 2015 May 20, at 17:39, Duncan P. N. Exon Smith <dexonsmith at apple.com> wrote: >> >> With just those four patches, memory usage went *up* slightly. Add in >> the 5th patch (which does #2 below), and we get an overall memory drop >> of 4%. > >

Two functions in DwarfDebug, addBlockByrefAddress() and addComplexAddress(), contain this snippet of code: // Decode the original location, and use that as the start of the byref // variable's location. const TargetRegisterInfo *RI = Asm->TM.getRegisterInfo(); unsigned Reg = RI->getDwarfRegNum(Location.getReg(), false); DIEBlock *Block = new (DIEValueAllocator) DIEBlock();

Hello All, I have created a set of patches that get dwarf debugging support working for the COFF object file. I also believe I have fixed what appears to be a bug in how line info sections are referred to from the DW_TAG_compile_unit DIE. I have run some basic tests, analyzed dumps of both the objects files and the final executables, and run a test program against mingw-gdb and everything looks

On Feb 12, 2011, at 2:07 AM, Nathan Jeffords wrote: > Hello All, > > I have created a set of patches that get dwarf debugging support working for the COFF object file. I also believe I have fixed what appears to be a bug in how line info sections are referred to from the DW_TAG_compile_unit DIE. I have run some basic tests, analyzed dumps of both the objects files and the final

Hi there, I think I've found a bug in the x86 JIT. I get an assertion failure when using thread-local variables and the fast emitter. It only happens with the JIT, the fast emiiter and thread-locals. (The IR passes the verifier) Here's the failure: X86CodeEmitter.cpp:516: void<unnamed>::Emitter::emitInstruction(const llvm::MachineInstr&, const llvm::TargetInstrDesc*):

Hi Jim, The idea of reducing the switching activity between the instructions works by reducing the hamming distance between tow consecutive binary strings across the basic block, or reducing the number of the different bits between two consecutive instructions. This is why I need the exact complete encoding in plain 0’s and 1’s, to be as precise as possible during the scheduling process. I did

Yes your absolutely right, the Opcode and the Operands in each machine instruction are sufficient to generate the final binary representation of the MachineInstruction but not exactly. If you take a look at the format of each MIPS instruction, you’ll see that there are some fixed bits for each instruction which are not available inside the machine instruction object –From what I saw so far-.

Hi all, when trying to build LLVM+Clang (r180247) on a BlueGene/Q, I get the following error message (multiple times): llvm[3]: Building PPC.td code emitter with tblgen llvm-tblgen: Unknown command line argument '-gen-emitter'. Try: '/homea/jjsc13/jjsc1301/.pool/.build/llvm_r180241/Release+Asserts/bin/llvm-tblgen -help' llvm-tblgen: Did you mean '-mc-emitter'? Has

Hi Jafar, That’s not quite what I meant. Why do you need to know the exact encoding at all? The instruction opcode+operands should have all the semantic information you need without ever looking at the actual encoding. -Jim On May 30, 2013, at 11:08 AM, Jafar J <pluck90 at hotmail.com> wrote: > Yes your absolutely right, the Opcode and the Operands in each machine instruction are

I need to represent each instruction with its (32-bit) binary encoding, and I reached to a conclusion that I could get the encoding through the MipsCodeEmitter. What I’m trying to do exactly is write a scheduler which tries to minimize the switching activity between the scheduled instructions in each basic block. One way to do that is by representing each instruction with its complete binary

On May 30, 2013, at 11:35 AM, Jafar J <pluck90 at hotmail.com> wrote: > Hi Jim, > > The idea of reducing the switching activity between the instructions works by reducing the hamming distance between tow consecutive binary strings across the basic block, or reducing the number of the different bits between two consecutive instructions. This is why I need the exact complete

Evan, Any plans to add it any time soon? It would be really appreciated. Evan Cheng wrote: > X86 JIT does not yet support TLS. > > Evan > On Jun 12, 2009, at 2:48 AM, Mark Shannon wrote: > >> Hi there, >> >> I think I've found a bug in the x86 JIT. I get an assertion failure >> when >> using thread-local variables and the fast emitter.

On 01/29/2014 12:14 PM, Rafael Espíndola wrote: > On 28 January 2014 19:56, reed kotler <rkotler at mips.com> wrote: >> I would like to make the following member of AsmPrinter be protected >> >> >> void EmitInlineAsm(StringRef Str, const MDNode *LocMDNode = 0, >> InlineAsm::AsmDialect AsmDialect = >>

Hi, Today I found a nice bug in the JIT global variable emitter. The problem may lead to an assert() failure when doing the following: 1) compile some function 2) emit a global variable 3) compile another function. an assert() may trigger in the JIT memory manager This happens because the JIT global variable emitter is using the MachineCodeEmitter::allocate() function, which uses memory