similar to: MachineModule pass

Yes, I have done exactly the same. The wawanalyzer is the same. I changed ARM.h and ARMTargetMachine.cpp in the tager/arm folder. then I make tool/llc and lib folder. On Tue, Nov 17, 2015 at 10:55 AM, John Criswell <jtcriswel at gmail.com> wrote: > On 11/17/15 12:16 AM, fateme Hoseini via llvm-dev wrote: > > Hi, > So, I run my pass in X86 target with llc command and it printed

Hi, So, I run my pass in X86 target with llc command and it printed out "hello****". Now I am trying to do the same pass for ARM target. So I did exactly what I did for X86 as mentioned in my previous posts. When I run the following command: llc -march=arm test.ll -o test nothing prints out. I did the same for MIPS target too and I got no result. Can anyone tell me what I'm doing

Hi, Is there a way to get instruction's offset at compile time with llvm for ARM? I am trying to create a map between instructions at compile time and this run-time info. Since PC is a relative value, I am trying to use the instruction's offset as a constant property of instruction to create this map. I think offset information should be available to create the executable, if so where to

Thank you so much. That helped alot. Fami On Wed, Nov 4, 2015 at 9:40 AM, John Criswell <jtcriswel at gmail.com> wrote: > On 11/3/15 7:54 PM, fateme Hoseini wrote: > > Dear John, > Thank you so much for your help. I looked at those documents. Could you > kindly answer the following questions: > > Does it mean that I have to make my own backend target in order to write

Hello everyone, I am trying to add checkpoints to my IR code. In order to do that I need to add this instruction: call void @m5_checkpoint(i64 0, i64 0) to some of the basic blocks in my benchmark. m5_checkpoint is a function defined for checkpointing in another simulator and is not included in my benchmark source code. So I need to create this instruction and I couldn't figure out how to do

Dear John, Thank you so much for your help. I looked at those documents. Could you kindly answer the following questions: Does it mean that I have to make my own backend target in order to write a machine pass even if I want to run a simple machinefunction pass? for example,if I want my pass to get MIPS instructions as an input, I have to copy all the files from mips target and add a file to it

Hello everyone, I am trying to write a code to do the following: 1. Get an ARM machine instruction 2. Find destination register of that instruction that has been written 3. set a bit in a vector, according to that register number. (Since it's ARM, I have a 15 bit vector) It means if I have : add r0, r1, r0 I want to get r0 as dest reg and set the index 0 of my vector to 1. I get my machine

Hi everyone, I am a LLVM newbie. I need to write a machinefunction pass for my project. This should be an analyzer of the machine code to do some profiling. I have written a couple of function passes for front end, but it seems they are completely different. I searched through forum and llvm documents, but couldn't find anything useful or questions were unanswered. Can anyone reference me to

Hi everyone, I am a new commer and I 'm tying to use LLVM to cross compile a code. I want to cross compile to MIPS and the host is the default x86. The more I read the document the more confused I get. I see documents on cross-compiling to ARM. But some install some gcc packages, while some use clang. I don't know where to start and how to do it. Is this just enough to run a command line

Hi, In the initial thread of the proposal for GlobalISel, I have mentioned that it may be interesting to have a kind of MachineModulePass. Marcello mentioned this would be useful for their current pipeline. I am interested in knowing: 1. If anyone else is interested for such concept? 2. What kind of information should we make accessible in an hypothetical MachineModule? I.e., how do you plan to

Hi Quentin, > On 22 Jan 2016, at 15:16, Quentin Colombet <qcolombet at apple.com> wrote: > 1. If anyone else is interested for such concept? yes, we are! (https://github.com/t-crest) > 2. What kind of information should we make accessible in an hypothetical MachineModule? I.e., how do you plan to use the MachineModulePass so that we make the right design decisions for the

Dear Tim, Thank you for your thorough reply. So, based on your reply I get every operand and check them to be (isDef && !isimplicit). Now my problem is that it gives me the physical register number.i.e, for example, instead of r0, it return %physreg66. Could you please help me on how to convert these physical register number to the ARM related register? I mean the 15 GPRs in ARM. Thank

Hello, Probably this may be too late to start thinking about this project but I think this is particularly useful feature for LLVM. A quick use I can think of this is Implementing Inter-procedural Register Allocation ( for Research purpose ). I have start looking at the code for MachineFunctionPass, I think currently MachineModule class is not available ( the project work will include that ) but

On 3/18/16 12:33 PM, Quentin Colombet via llvm-dev wrote: > Hi Vivek, > >> On Mar 16, 2016, at 1:00 PM, vivek pandya via llvm-dev >> <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: >> >> Hello, >> >> Probably this may be too late to start thinking about this project >> but I think this is particularly useful

Ryan Taylor via llvm-dev <llvm-dev at lists.llvm.org> writes: > r0 gets overwritten inside the loop (assuming dst, src, src), is ldr > r0, [r5] needed to initialize r0 for the loop at each iteration? Register allocation should handle that if the load is hoisted. I'm with the others. The printf is the most likely culprit. -0David > On Thu, Mar 28, 2019

*Vivek Pandya* On Fri, Mar 18, 2016 at 10:03 PM, Quentin Colombet <qcolombet at apple.com> wrote: > Hi Vivek, > > On Mar 16, 2016, at 1:00 PM, vivek pandya via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > Hello, > > Probably this may be too late to start thinking about this project but I > think this is particularly useful feature for LLVM. >

> On May 10, 2016, at 6:06 PM, Hal Finkel <hfinkel at anl.gov> wrote: > > > > From: "vivek pandya" <vivekvpandya at gmail.com> > To: "llvm-dev" <llvm-dev at lists.llvm.org>, "Tim Amini Golling" <mehdi.amini at apple.com>, "Hal Finkel" <hfinkel at anl.gov> > Cc: "Quentin Colombet" <qcolombet

> On Mar 8, 2016, at 11:50 AM, Eric Christopher <echristo at gmail.com> wrote: > > > > > I could attach a patch, but first i’d really like to know if anyone is fundamentally opposed to this. > > > Not necessarily. I think that any information that isn't being serialized in MI right now for a function could be as well. Definitely something for GlobalISel

Hello Community, I have submitted my draft proposal for this project on the summer of code web site and shared it with the community. Please take a look at it and suggest/ comment some modifications. I have already done some study on the relevant code. I will still do some more before the final submission but this is more of designing challenge please help ! Sincerely, *Vivek Pandya*

> On May 15, 2016, at 12:43 AM, vivek pandya <vivekvpandya at gmail.com> wrote: > > > > Vivek Pandya > > > On Wed, May 11, 2016 at 9:43 AM, Mehdi Amini <mehdi.amini at apple.com <mailto:mehdi.amini at apple.com>> wrote: > >> On May 10, 2016, at 6:06 PM, Hal Finkel <hfinkel at anl.gov <mailto:hfinkel at anl.gov>> wrote: >>