similar to: Vectors in Sparc

Hi, Does anyone have any direction for me on testing a back-end pre-emit pass independently of other passes? The pass I'm looking at is a MachineFunctionPass, so the code is already using target-specific instructions. What I'm really looking to do is to see that the pass is correctly converting certain target-specific instructions sequences into other sequences, but I'm unsure how I

Hi, I've discovered a problem on Sparc processors (specifically, LEON, but I suspect but can't verify that it also happens on all Sparc processors). The problem is, or appears to be with using double values in Sparc (32 bit). Specifically, double values are not being loaded into registers correctly within a function using va_args. Only half the value is loaded (i.e. 32, rather than 64

Hi, I'm trying to implement __builtin_setjmp / __builtin_longjmp for Sparc processors. I think I'm very close, but I can't work out how to issue BuildMI-type instructions to load the address of the recovery location (set in setjmp) into a register using the SETHI / OR combination. I can't see any equivalent code anywhere else in Sparc. I imagine this is similar if I try to make a

I'm trying to define a multiply-accumulate instruction for the LEON processor, a Subtarget of the Sparc target. The documentation for the processor is as follows: === To accelerate DSP algorithms, two multiply&accumulate instructions are implemented: UMAC and SMAC. The UMAC performs an unsigned 16-bit multiply, producing a 32-bit result, and adds the result to a 40-bit accumulator made

Hi, in section B.29. (Write State Register Instructions) of 'The SPARC Architecture Manual Version 8' it is said that the "The write state register instructions are delayed-write instructions." The Y-register is a state-register. Furthermore in the B.29-secion there is a programming note saying: MULScc, RDY, SDIV, SDIVcc, UDIV, and UDIVcc implicitly read the Y register.

I've been looking to see if there's a way to get the instruction below (SMAC) emitted from a higher-level construct, but I'm starting to think this is unrealistic. To do so, I'd have to tie-in two other instructions: Firstly, clearing the ASR18 and Y register somewhere near the start of the method, then copying out the value of these registers somewhere near the end of the method,

Hi, I have a task to complete and I'm getting stuck. I can't find anything comparable in the documentation. The shortest explanation I can give is as follows: I need to use double-precision floating point values for floating-point multiplies. I'll not go into why: That would take the discussion away from the essential problem. E.g. Replace: fmuls %f20,%f21,%f8 with the

Hello... I noticed from the list that puppet is not ready for ruby 1.9.2 yet. I''m working at a ruby shop so I gave a shot at building ruby 1.9.2 rpms with supporting gems for RHEL/CentOS. I have ruby-1.9.2 rpms that replace the vendor rpms and ruby192 rpms that install in parallel with the vendor rpms. Is anyone interested in using these rpms to get puppet working with 1.9.2 and/or

The following problem occurs in R 1.4.0 and 1.3.1 for Windows95, but not in R 1.2.0 for Windows95. The problem does not occur in R 1.4.0 for Linux PC, Linux Alpha and HP-UX. Sometimes, the type of 'Size' of an object of type 'dist' changes from integer into double. Running cmdscale on such a 'dist' object gives invalid results. I don't know what should be considered

Dear everyone, It's time for the release notes nagging email. We have release notes for LLVM, Clang, clang-tools-extra, lld, and Polly. (If there are more, please let me know.) Most of these are pretty empty files; see e.g. the LLVM one at [1]. The internet does read these notes when we release, so please help make them informative! If you made any interesting changes during the past six

Hi, I'm implementing __builtin_setjmp and __builtin_longjmp for Sparc 32 bit processors (64 bit later, time allowing). I'm basing the code on the PowerPC version, which itself is based on the X86 version. This code is very nearly working, and I've had it working for -O0 optimisation (with a slightly different version to that below), so I know it's close. However, the PowerPC

Ok, I've been looking at this for hours and can't figure it out. I know I'm missing something obvious. I've been spending the past few days beefing up the vector support in the C Backend. This should help us debug vector code that's miscompiled. But gcc doesn't like this fragment: ((double *)(&llvm_cbe_r1147))[0u] = (((llvm_cbe_r1146__BITCAST_TEMPORARY.Int64 =

Hi Devs, Consider below testcase. $cat test.cpp #include <vector> #include<type_traits> typedef int _int4 __attribute__((vector_size(16))); typedef union{ int data[4]; struct {int x, y, z, w;}; _int4 vec; } int4; typedef int4 int3; int main() { static_assert(std::alignment_of<int4>::value <= alignof(max_align_t), "over aligned!"); } $clang++ -m32 error:

Help: How to define vector element type bool (v8i1) in C builtin function hello everyone,I have defined intrinsic function like this: def int_mips_add_32 : GCCBuiltin<"__builtin_dongxin_add_32">, Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty,llvm_v8i1_ty]>; Then I write a test code : typedef int v4i32 __attribute__ ((vector_size(16))); typedef bool v8i1

Hi Everyone, I'm happy to say that we just got approval to open source the new C front-end for LLVM we've been working on. The goal of this work is to provide a high quality front-end for LLVM that is built with the same principles as the rest of LLVM (it is built as a set of reusable libraries, integrates well with rest of the LLVM architecture, same license, etc). Among other

Hi All, If the target supports quad-register R0:R1:R2:R3 (Rn is 32-bit register), is it possible mapping quad-register to v4i32 so that the following example work? typedef int v4si __attribute__ ((vector_size (16))); void foo(v4si i) { v4si j = i; } I don't know how to write CallingConv.td to represent the concept of occupying quad-register R0:R1:R2:R3 once seeing

Subject: How to define vector element type bool in builtin function hello everyone,I have defined intrinsic function like this: def int_mips_add_32 : GCCBuiltin<"__builtin_dongxin_add_32">, Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty,llvm_v8i1_ty]>; Then I write a test code : typedef int v4i32 __attribute__ ((vector_size(16))); typedef bool v8i1

Hi Bruce, Thanks for response. I also think it is not good way. Do you have the other ways to legalize it? Thanks, JinGu Kang 2016-02-01 13:11 GMT+00:00 Bruce Hoult <bruce at hoult.org>: > In fact this is a pretty bad legalizing/lowering because you only need to > load and edit for the first and last values in the vector. The other words > are completely replaced and don't

Hi Krzysztof, Thanks for response. The method is working almost of test cases which use load and store instructions connected with chain. There is other situation. Let's look at a example as follows: typedef unsigned short int UV __attribute__((vector_size (8))); void test (UV *x, UV *y) { *x = *y / ((UV) { 4, 4, 4, 4 }); } The target does not support vector type so CodeGen tries to

My current implementation uses target intrinsic to represent math functions. The current issue with this is that the math functions must support up to vec16 but the backend only supports up to vec4. Is there a way to split a target intrinsic into multiple legal intrinsic of the smaller vector type? This is similar to the splitVectorOp in legalizeDag but on intrinsic. Thanks, Micah