similar to: get instruction destination register

Dear Tim, Thank you for your thorough reply. So, based on your reply I get every operand and check them to be (isDef && !isimplicit). Now my problem is that it gives me the physical register number.i.e, for example, instead of r0, it return %physreg66. Could you please help me on how to convert these physical register number to the ARM related register? I mean the 15 GPRs in ARM. Thank

Hi, Is there a way to get instruction's offset at compile time with llvm for ARM? I am trying to create a map between instructions at compile time and this run-time info. Since PC is a relative value, I am trying to use the instruction's offset as a constant property of instruction to create this map. I think offset information should be available to create the executable, if so where to

Yes, I have done exactly the same. The wawanalyzer is the same. I changed ARM.h and ARMTargetMachine.cpp in the tager/arm folder. then I make tool/llc and lib folder. On Tue, Nov 17, 2015 at 10:55 AM, John Criswell <jtcriswel at gmail.com> wrote: > On 11/17/15 12:16 AM, fateme Hoseini via llvm-dev wrote: > > Hi, > So, I run my pass in X86 target with llc command and it printed

Hi, So, I run my pass in X86 target with llc command and it printed out "hello****". Now I am trying to do the same pass for ARM target. So I did exactly what I did for X86 as mentioned in my previous posts. When I run the following command: llc -march=arm test.ll -o test nothing prints out. I did the same for MIPS target too and I got no result. Can anyone tell me what I'm doing

Thank you so much. That helped alot. Fami On Wed, Nov 4, 2015 at 9:40 AM, John Criswell <jtcriswel at gmail.com> wrote: > On 11/3/15 7:54 PM, fateme Hoseini wrote: > > Dear John, > Thank you so much for your help. I looked at those documents. Could you > kindly answer the following questions: > > Does it mean that I have to make my own backend target in order to write

Hello everyone, I am trying to add checkpoints to my IR code. In order to do that I need to add this instruction: call void @m5_checkpoint(i64 0, i64 0) to some of the basic blocks in my benchmark. m5_checkpoint is a function defined for checkpointing in another simulator and is not included in my benchmark source code. So I need to create this instruction and I couldn't figure out how to do

Dear John, Thank you so much for your help. I looked at those documents. Could you kindly answer the following questions: Does it mean that I have to make my own backend target in order to write a machine pass even if I want to run a simple machinefunction pass? for example,if I want my pass to get MIPS instructions as an input, I have to copy all the files from mips target and add a file to it

Hi everyone, I am a LLVM newbie. I need to write a machinefunction pass for my project. This should be an analyzer of the machine code to do some profiling. I have written a couple of function passes for front end, but it seems they are completely different. I searched through forum and llvm documents, but couldn't find anything useful or questions were unanswered. Can anyone reference me to

Hi everyone, I am a new commer and I 'm tying to use LLVM to cross compile a code. I want to cross compile to MIPS and the host is the default x86. The more I read the document the more confused I get. I see documents on cross-compiling to ARM. But some install some gcc packages, while some use clang. I don't know where to start and how to do it. Is this just enough to run a command line

Hello everyone, As I mentioned in my previous posts,I am using a machinefunction pass to find all the loops in the program and do some analysis on them. I have completed my pass now and it works correctly. but the only issue is that,I have noticed that if I have two functions in my program, and one of them is part of the loop for another one ,by using runonmachinefunction(), I will get one loop

Hi, I think I've found a bug in this method. I ran it on an MI which already had two implicit-use operands, and which defined a register with a subregindex, ie reg::lo16. For the def-operand, with a subregindex, an implicit-use operand was added with this code: VirtUseOps.insert(VirtUseOps.begin(), MI.getNumOperands()); MI.addOperand(MachineOperand::CreateReg(VirtReg,

Ryan Taylor via llvm-dev <llvm-dev at lists.llvm.org> writes: > r0 gets overwritten inside the loop (assuming dst, src, src), is ldr > r0, [r5] needed to initialize r0 for the loop at each iteration? Register allocation should handle that if the load is hoisted. I'm with the others. The printf is the most likely culprit. -0David > On Thu, Mar 28, 2019

On Oct 7, 2011, at 8:14 AM, Jonas Paulsson wrote: > Hi, > > I think I've found a bug in this method. > > I ran it on an MI which already had two implicit-use operands, and which defined a register with a subregindex, ie reg::lo16. > > For the def-operand, with a subregindex, an implicit-use operand was added with this code: > >

Hi, Is it possible to add a spill code (a pair of store /load ) to the machinecode in a pass before the instruction emitter? If so, how can I calculate the address (offset to the sp) for the spill store/load instructions? Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hi Does LLVM dynamically run the program to obtain profiling information like branch weight? if so, can we access the information regarding this run like the number of instructions that have been executed dynamically between two specific points of the program? Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hello, Consider this code (this is all after register allocation): R0<def> = ... R0 // Set lower half (based on the previous value) R1<def> = ... // Set upper half ... = R0_R1 // Use the pair It is my understanding that the use of the whole pair will need to have some sort of a reaching def, i.e. the code will need at least those flags: R0<def> =

I have two questions regarding MachineMemOperands and dependence information. Q1) I noticed that MachineMemOperands are lost when two LDRs are combined and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps. (before optimization) %reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0; mem:LD4[%uglygep10] %reg1054<def> = LDR %reg1030, %reg0, 4104, pred:14,

Hi, I think I discovered a major armv7 optimization bug in Clang. I create a simple test case which exhibits the issue. When you compile the attached file for armv7 with optimizations turned on (O2, O3 or Os), the binary generated led to a crash. The issue can't be reproduced when using GCC 4.2. It can't be reproduced with Clang when the optimization is turned off (O0). This issue can be

On Sep 7, 2010, at 10:48 AM, Akira Hatanaka wrote: > I have two questions regarding MachineMemOperands and dependence information. > > Q1) I noticed that MachineMemOperands are lost when two LDRs are combined and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps. > > (before optimization) > %reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0;

Hi all, I have a package that is specific to a task I was repetitively using a few years ago. I now needed to run it again with new data. However I am told it was built with an older version or R and will not work. How can I tweak the package so it will run on 11.1? It was a one-off product and has not been maintained. Is there a way to "unpackage" it and repackage it to work? I