Displaying 5 results from an estimated 5 matches similar to: "Immediate value boundary checking"
2018 May 15
1
[tablegen] anonymous def not fully instantiated
The following is an extraction from the Operand class hierarchy of Target.td. I am trying to define a parameterized version of AsmOperandClass with a passed-in bit size.
// from Target.td
class AsmOperandClass {
string Name;
}
class Operand {
AsmOperandClass ParserMatchClass;
}
// A parameterized AsmOperandClass
class myAsmOperandClass<int n> : AsmOperandClass {
string Name =
2019 Mar 25
2
Printing PC-relative offsets - how to get the instruction length?
Hi
In my MC6809 backend, in llvm/lib/Target/MC6809/InstPrinter/MC6809InstPrinter.cpp, I have the routine
void MC6809InstPrinter::printPCRelImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNo);
ZZ
if (Op.isImm()) {
int64_t Imm = Op.getImm() + 2; <<<========================
O << "$";
if (Imm
2015 Dec 14
2
Tablegen definition question
Hi,
That's what the DecoderMethod is for. Similarly ParserMatchClass for the
asm parser and PrintMethod for the asm printer:
def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; }
def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),
(ops (i32 14), (i32 zero_reg))> {
let PrintMethod = "printPredicateOperand";
2015 Dec 14
2
Tablegen definition question
Hello James,
that was also what I've planned to do but just wasn't sure. Thanks for
that.
On Mon, Dec 14, 2015 at 11:52 AM, James Molloy <james at jamesmolloy.co.uk>
wrote:
> Hi,
>
> You can't nest operands like that - it must be a flattened list. So:
>
> def *Xpred* : PredicateOperand<OtherVT, (ops *i32imm, i32imm*, i32imm),
> (ops (i32 14), (i32
2016 Feb 08
2
LLVM Weekly - #110, Feb 8th 2016
LLVM Weekly - #110, Feb 8th 2016
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