similar to: Hexagon, DFAPacketzier and dependency pruning

In the Hexagon backend we originally treated CFI instructions as "solo", > i.e. they could not be packetized with any other instruction. Now we > simply delay the generation of these instructions until after > packetization. The reason for this is that two instructions that could be > packetized together were not packetized together if there was an CFI > instruction in

I'm using a Hexagon's packetizer as an example to packetize instructions for my custom VLIW. The problem that I'm facing is that my target as it turns out doesn't have all the instructions expanded by the time packetization happens (for example I have a RET instruction which gets expanded into a write to a register and a jump/branch). I'm wondering if Hexagon is experiencing

> Does the instruction that is being added have an itinerary associated with > it? > So I checked again, and it turns out that it does have an itinerary associated with it. However it is a pseudo instruction. Does the packetizer do something special with the pseudo instructions? I didn't see any special code, but I could have missed it. -- R -------------- next part --------------

Hi, Here's a patch for Hexagon Packetizer for review. This patch does not yield any warnings. Sirish -- Qualcomm Innovation Center, Inc is a member of Code Aurora Forum -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: HexagonPacketizer.patch URL:

Hi, I'm trying to use the VLIWPacketizerList to schedule instructions for the R600 target, and I'm running into this assertion failure: ScheduleDAGInstrs.cpp:558: Cannot schedule terminators or labels! I think I might not be using the VLIWPacketizerList class correctly. I've attached my code to this email. Can anyone spot what I'm doing wrong? Also, I had to add a LiveIntervals

On Wed, Nov 18, 2015 at 6:44 AM, Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 11/17/2015 6:51 PM, Rail Shafigulin via llvm-dev wrote: > >> I'm using a Hexagon's packetizer as an example to packetize instructions >> for my custom VLIW. The problem that I'm facing is that my target as it >> turns out doesn't have all the

Hi Anshu, no, I did not fill a bug report. It is not so easy to make the code fail noticeably; during Hexagon CodeGen tests it happens silently and tests pass. I am working on another VLIW backend which uses DFAPacketizer and compiling llvm with gcc-4.4 makes it segfault, but with gcc-4.7 the bug gets hidden again (it still happens, but values after DFAStateEntryTable in memory are such that

Hi, I'm working on a custom top-down post RA scheduler which builds bundles at the same time for our VLIW processor. I've borrowed most of the implementation from the resource priority queue implemented for the existent VLIW scheduler but applied to the context of MI scheduling. Basically, instructions that are likely to be bundled must be scheduled first (i.e. get higher priority).

Hi all, I have found what I think it is a bug in DFAPacketizer::ReadTable. When finding NextStateInTable to cache all transitions belonging to a state into CachedTable, ReadTable does not check bounds: unsigned ThisState = DFAStateEntryTable[state]; | unsigned NextStateInTable = DFAStateEntryTable[state+1]; which makes NextStateInTable get a random value when state == <last state in

Hi all, I'd recommend Andy Trick be made code owner of "instruction scheduling" (including MI, pre-RA, and post-RA schedulers). I am also recommending Nadav Rotem be made code owner of "loop vectorizer". Evan

I'm considering writing more-detailed itineraries for some PowerPC CPUs that use the 'traditional' instruction grouping scheme. In essence, this means that multiple instructions will stall in some pipeline stage until a complete group is formed, then all will continue. I expect to provide CPU-specific code to help determine when the currently-waiting instructions would form a group.

On Nov 13, 2012, at 2:59 PM, Evan Cheng <evan.cheng at apple.com> wrote: > Hi all, > > I'd recommend Andy Trick be made code owner of "instruction scheduling" (including MI, pre-RA, and post-RA schedulers). I am also recommending Nadav Rotem be made code owner of "loop vectorizer". Sergei Larin can take ownership of VLIW scheduling. Most of the support

Hi Jonas, > It is interesting to find this in the ARM backend, considering your answer. The ARM backend doesn't use the DFA packetizer. It's only used by Hexagon. At this point, there is no plan to address thisin the DFA packetizer since none of the supported targets needthe functionality. Thanks -Anshu --- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,

Hi, I am extending LLVM for HPC applications. As one of them, I am trying to make MachinePipeliner available on AArch64 + Scalable Vector Extension environment. MachinePipeliner is currently used only by Hexagon CPU. Since it is a very portable implementation, I think that it will actually work just by adding a little code for many CPUs(See Code [2]). The current MachinePipeliner is written on

Hi Carlos, Thanks for identifying the bug. I'll confirm and fix. Is there a bug report open for this? -Anshu --- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation On 12/10/2012 4:48 AM, Carlos Sánchez de La Lama wrote: > Hi all, > > I have found what I think it is a bug in DFAPacketizer::ReadTable. > > When finding

Sergei, Thank you for your attention. My target is a custom VLIW DSP. I am not sure dependency dag is correct when it gets scheduled and packetized. Months ago, I submitted a bug at http://llvm.org/bugs/show_bug.cgi?id=17894 which explained more details. I am not sure my understanding of this bug is proper, but modified my local codes this way and it works for my target when scheduling and

Carlos, I committed a fix in r169783. Thanks for catching this. However, I could not reproduce an invalid read or a segfault even with fadd.ll. Is there a test case you can check in that reproduces this bug? Even if the segfault occurs intermittently, that's better than no test case at all. Thanks -Anshu --- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by

Is there a way to convert between SchedMachineModel and Itineraries? I was trying to write a very simple VLIW packetizer (Hexagon was my starting point). It turns out that current DFAPacketizer is using itineraries, but my schedule is based on SchedMachineModel (I was recommended to use it since the itineraries are being phased out). I was wondering if there is an automated tool that would

On Jun 11, 2012, at 9:30 AM, Hal Finkel <hfinkel at anl.gov> wrote: > I'm considering writing more-detailed itineraries for some PowerPC CPUs > that use the 'traditional' instruction grouping scheme. In essence, > this means that multiple instructions will stall in some pipeline stage > until a complete group is formed, then all will continue. > > I expect to

Hi Anshu, I got a testbench which fails (and segfaults) consistently with an environment (gcc + os) conveniently preserved in a virtual machine. I will confirm that it is gone there and report. Thanks for the fix :) Carlos 2012/12/10 Anshuman Dasgupta <adasgupt at codeaurora.org> > Carlos, > > I committed a fix in r169783. Thanks for catching this. > > However, I could