similar to: DFAPacketzer, Hexagon and bundles with 1 instruction

Displaying 20 results from an estimated 300 matches similar to: "DFAPacketzer, Hexagon and bundles with 1 instruction"

2016 Jan 20
2
a bundle with one instruction
Is there a way to place a bundle a BUNDLE instruction into a packet with one instruction? Current code to end packet doesn't handle this case: // endPacket - End the current packet, bundle packet instructions and reset // DFA state. void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB, MachineInstr *MI) { if (CurrentPacketMIs.size() > 1) {
2015 Nov 17
2
DFAPacketzer, Hexagon and bundles with 1 instruction
> No. An instruction on its own is equivalent to a bundle with that > instruction only. Also, a BUNDLE must have at least 2 instructions. > > -Krzysztof > > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted > by The Linux Foundation > _______________________________________________ > LLVM Developers mailing list > llvm-dev at
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
Sure I will split it and put it in two patches. Give me few hours. I need to test those patches. Sirish On 4/19/2012 8:40 AM, Tom Stellard wrote: > On Wed, Apr 18, 2012 at 11:18:05PM -0500, Sirish Pande wrote: >> Hi, >> >> Here's a patch for Hexagon Packetizer for review. This patch does >> not yield any warnings. >> > Would it be possible to split this
2016 Oct 28
2
Understanding and Cleaning Up Machine Instruction Bundles
> On Oct 27, 2016, at 5:23 PM, Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > On 10/27/2016 4:33 PM, Matthias Braun via llvm-dev wrote: >> >> In fact I am not sure why you would even wait with the finalization and do it >> in a separate pass rather than doing it immediately after forming the bundle. >> Using the pass today does not
2016 Oct 28
0
Understanding and Cleaning Up Machine Instruction Bundles
On 10/27/2016 4:33 PM, Matthias Braun via llvm-dev wrote: > > In fact I am not sure why you would even wait with the finalization and do it > in a separate pass rather than doing it immediately after forming the bundle. > Using the pass today does not even work as the MachineVerifier will reject the > intermediate unfinalized state (missing internal read markers). I'd suggest to
2013 Mar 14
0
[LLVMdev] Hexagon: removing support for Hexagon-v2 and Hexagon-v3
On 03/14/2013 12:51 PM, Anshuman Dasgupta wrote: > I wanted to give everybody a heads-up on upcoming commits for the > Hexagon backend. We will be removing support for older versions of the > Hexagon architecture - specifically Hexagon-v2 and Hexagon-v3. These are > no longer being used by compiler users. Matthew Curtis has committed the > first clang patch to remove driver support
2012 Mar 30
1
[LLVMdev] VLIWPacketizerList: failing to schedule terminators
On Thu, Mar 29, 2012 at 03:51:10PM -0700, Andrew Trick wrote: > > On Mar 29, 2012, at 1:18 PM, Tom Stellard <thomas.stellard at amd.com> wrote: > > > On Thu, Mar 29, 2012 at 02:57:27PM -0500, Sergei Larin wrote: > >> Tom, > >> > >> I do not have your call stack, but packetizer calls > >> ScheduleDAGInstrs::buildSchedGraph to create
2013 Mar 14
2
[LLVMdev] Hexagon: removing support for Hexagon-v2 and Hexagon-v3
I wanted to give everybody a heads-up on upcoming commits for the Hexagon backend. We will be removing support for older versions of the Hexagon architecture - specifically Hexagon-v2 and Hexagon-v3. These are no longer being used by compiler users. Matthew Curtis has committed the first clang patch to remove driver support for these versions. There will be follow-up patches on the LLVM side
2012 Mar 29
0
[LLVMdev] VLIWPacketizerList: failing to schedule terminators
On Mar 29, 2012, at 1:18 PM, Tom Stellard <thomas.stellard at amd.com> wrote: > On Thu, Mar 29, 2012 at 02:57:27PM -0500, Sergei Larin wrote: >> Tom, >> >> I do not have your call stack, but packetizer calls >> ScheduleDAGInstrs::buildSchedGraph to create dependency model. If this is >> the first time you use the new MI sched infrastructure (like your
2013 Feb 04
2
[LLVMdev] Asserts in bundleWithPred() and bundleWithSucc()
Jakob, > The intention was to identify code that may have been converted from > the old style a little too quickly. I wanted to avoid bugs from a > global s/setIsInsideBundle/bundleWithPred/g search and replace. This is a good intent. Maybe a bit temporal but sound nevertheless. > finalizeBundle is calling 'MIBundleBuilder Bundle(MBB, FirstMI, > LastMI)' which ought to
2012 Apr 19
1
[LLVMdev] Hexagon Patch for
Hi, Here's a Hexagon patch for replacing transfer/copy instructions to combine for review. This patch does not yield any warnings on Hexagon, Arm and X86 build on Linux. This work is by Arnold Schwaighofer. Sirish -- Qualcomm Innovation Center, Inc is a member of Code Aurora Forum -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name:
2012 Apr 19
0
[LLVMdev] Patch for Hexagon Architectural feature, New value jump.
Here's a Hexagon patch for Hexagon New Value Jump instructions for review. This patch does not yield any warnings on Hexagon, Arm and X86 build on Linux. Sirish -- Qualcomm Innovation Center, Inc is a member of Code Aurora Forum -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: HexagonNewValueJump.patch URL:
2012 Apr 19
0
[LLVMdev] Hexagon cfe patch for V5- floating point support.
Here's a Hexagon cfe patch for floating point support. Please take some time to review this patch. This patch does not yield any warnings on Hexagon, Arm and X86 build on Linux. Sirish -- Qualcomm Innovation Center, Inc is a member of Code Aurora Forum -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: HexagonV5-FP-Support-cfe.patch
2012 Apr 19
0
[LLVMdev] Hexagon llvm patch for V5- floating point support.
Here's a Hexagon llvm patch for floating point support. Please take some time to review this patch. This patch does not yield any warnings on Hexagon, Arm and X86 build on Linux. Sirish -- Qualcomm Innovation Center, Inc is a member of Code Aurora Forum -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: HexagonV5-FP-Support-llvm.patch
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
No test cases for a 500k patch? -eric On Apr 18, 2012, at 9:18 PM, Sirish Pande wrote: > Hi, > > Here's a patch for Hexagon Packetizer for review. This patch does not yield any warnings. > > Sirish > > -- > Qualcomm Innovation Center, Inc is a member of Code Aurora Forum > > <HexagonPacketizer.patch>_______________________________________________
2012 Apr 20
2
[LLVMdev] Hexagon Test cases.
Here's a patch that contains Hexagon Test cases. Please review. Sirish -- Qualcomm Innovation Center, Inc is a member of Code Aurora Forum -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: HexagonTestCases.patch URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120420/eb32dede/attachment.ksh>
2012 Apr 20
0
[LLVMdev] Hexagon Test cases.
On Apr 20, 2012, at 1:58 PM, Sirish Pande <spande at codeaurora.org> wrote: > Here's a patch that contains Hexagon Test cases. Please review. You can't include these in the patches that they're supposed to go along with? -eric
2012 Apr 20
1
[LLVMdev] Hexagon Test cases.
Sure I can do that. In that case, let me recreate all the patches (along with the test cases) and put up the patches for review. sirish On 4/20/2012 4:16 PM, Eric Christopher wrote: > On Apr 20, 2012, at 1:58 PM, Sirish Pande<spande at codeaurora.org> wrote: > >> Here's a patch that contains Hexagon Test cases. Please review. > You can't include these in the
2012 Jul 03
0
[LLVMdev] target hexagon and sparcv9 lead to llc crack
Hi, > (4) llc -march=hexagon test.ll -o test.s > > '' is not a recognized processor for this target (ignoring processor) > 0 llc 0x08c2512b > Stack dump: > 0. Program arguments: llc -march=hexagon test.ll -o test.s > 1. Running pass 'Function Pass Manager' on module 'test.ll'. > 2. Running pass 'Hexagon DAG->DAG Pattern Instruction
2012 Aug 03
1
[LLVMdev] TableGen related question for the Hexagon backend
On Fri, Aug 3, 2012 at 12:02 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: >> Why wouldn't it be acceptable for the *.td files defining the instructions >> and the relations between them to be generated and not written by hand? > > Because it defeats the purpose of open source. > > It would be impossible to improve the way Hexagon models instructions