similar to: DFAPacketizer assert failure

> > It's hard to make a guess based on that assertion alone. Apparently there > is no transition in the DFA for these values. > > Do the arguments (e.g. CurrentState and FuncUnits) look reasonable? FuncUnits = 0 CurrentState = 0 StateTrans = {first = 0, second = 0} I understand that there is something wrong with the state machine but I can't figure out what exactly. My

Hi, I am having problems writing the ProcessorItineraries list. As instructions on my VLIW target have varying size I want to model both cpu units and bundle bits as FUs. The following does not work, to my surprise: InstrItinData<ALU, [InstrStage<1, [BITS1,BITS2, BITS3, BITS4], 0>, InstrStage<1, [ALU1, ALU2]>]> I want to express that there are

Jonas, At this point, the DFA packetizer models a simple VLIW architecture and does not accommodate multiple stages. That's the reason for the behavior you're seeing. -Anshu --- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation *From:*llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] *On Behalf Of *Jonas

Hi, I looked a bit through the mail archives, and found this question answered in Oct 2011 (see below). It is interesting to find this in the ARM backend, considering your answer. Can you give more information about for example is this a temporary deficiency in the DFAPacketizer? What is the IIC_iMOVi itinerary doing below? Thanks, Jonas Thu Oct 6 15:11:25 CDT 2011: Hello Hal. > Is there

Hi sam, On 12/06/2012 17:30, sam wrote: > Hi Ivan, > > The assertion was happening because I wasn't checking after the first > attempt failed. The first packet was failing and so it was ended, and > then the packetizer attempted to add it to the next packet without > checking for available resources. However this highlights probably the > real problem - my packetizer

Hi Sam, On 12/06/2012 15:33, sam wrote: > Hi, > > I'm trying to get the DFAPacketizer to work for my target but with any > instruction I get the > 'Assertion `CachedTable.count(StateTrans) != 0' failed' error and it crashes > out before packeting a single instruction. Do you reserve some resource without verification? Note that reserveResources() should be

Hi Ivan, The assertion was happening because I wasn't checking after the first attempt failed. The first packet was failing and so it was ended, and then the packetizer attempted to add it to the next packet without checking for available resources. However this highlights probably the real problem - my packetizer is unable to find resources for the first instruction, or any of my

Hi Anshu, Would there be any interest in extending this algorithm to handling more extensive models, such as VLIW scheduling based on FU's and bundle space... ie handle multiple stages ? I might do it and commit, if there is acceptance and guidance... Jonas ________________________________ From: Anshuman Dasgupta [mailto:adasgupt at codeaurora.org] Sent: Tuesday, February 12, 2013 4:47 PM

Hi Jonas, > It is interesting to find this in the ARM backend, considering your answer. The ARM backend doesn't use the DFA packetizer. It's only used by Hexagon. At this point, there is no plan to address thisin the DFA packetizer since none of the supported targets needthe functionality. Thanks -Anshu --- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,

I missed last 2 commits made by Alexey. Following his advices, I updated the patch. It should be ok now. Ivan On 27/06/2012 21:42, Anshuman Dasgupta wrote: > Committed in r159281. > > -Anshu > > > On 6/26/2012 3:04 AM, Ivan Llopard wrote: >> Hi Anshu, >> >> I don't have commit access. It applies correctly on trunk, I've just >> checked it.

Hi, I'm trying to get the DFAPacketizer to work for my target but with any instruction I get the 'Assertion `CachedTable.count(StateTrans) != 0' failed' error and it crashes out before packeting a single instruction. I have a *GenDFAPacketizer.inc file and my packetizer pass checks that the table is not empty before proceeding. I also have a schedule file with my functional

Committed in r159281. -Anshu On 6/26/2012 3:04 AM, Ivan Llopard wrote: > Hi Anshu, > > I don't have commit access. It applies correctly on trunk, I've just > checked it. Could you please commit it? > > Ivan > > On 26/06/2012 04:44, adasgupt at codeaurora.org wrote: >> Hi Ivan, >> >> Sorry, I should have been more explicit in my last email. The

Hi Anshu, I don't have commit access. It applies correctly on trunk, I've just checked it. Could you please commit it? Ivan On 26/06/2012 04:44, adasgupt at codeaurora.org wrote: > Hi Ivan, > > Sorry, I should have been more explicit in my last email. The patch looks > good to me. Please check that it applies on trunk and go ahead and commit. > > Thanks > -Anshu

Hello, I've made a backend for Tile64 processor as my master's thesis. Of course, there is a lot to do in order to harness all the power of the processor, but LLVM programs already can be compiled to tile assembly. If anyone interested in the backend, just let me know and I release the code on our project site. One way to improve my backend is to utilize its ILP capabilities, so I'd

Hi Ivan, The patch looks good to me. I have a couple of minor comments: +void State::AddInsnClass(unsigned InsnClass, Add a top level comment describing the function + std::map<State*, std::set<Transition*, ltTransition>, ltState> stateTransitions; You should be able to use SmallSet here. Also, this line exceeds 80 columns. On a related note, is the CachedTable mechanism in

> Thanks for reviewing this. I added a top comment for AddInsnClass and I fixed the violation of column numbers. Great. Looks good to me. > IMO, it wil be nice to keep it alive for performance comparisons. Given the overall performance > is rather determined by transition searches on the current state, for small DFA tables may not be a win > and it may still be the case for

Hi Ivan, Sorry, I should have been more explicit in my last email. The patch looks good to me. Please check that it applies on trunk and go ahead and commit. Thanks -Anshu > Hi Anshu, > > Just in case you have forgotten this thread ;-). Is this patch ok to > commit or does it not apply to trunk properly ? > I can fix it if that's the problem. > > Ivan > > On

Hi Anshu, Thanks for reviewing this. I added a top comment for AddInsnClass and I fixed the violation of column numbers. On 15/06/2012 21:31, Anshuman Dasgupta wrote: > Hi Ivan, > > The patch looks good to me. I have a couple of minor comments: > > +void State::AddInsnClass(unsigned InsnClass, > Add a top level comment describing the function > > + std::map<State*,

Hi Anshu, Just in case you have forgotten this thread ;-). Is this patch ok to commit or does it not apply to trunk properly ? I can fix it if that's the problem. Ivan On 20/06/2012 19:33, Anshuman Dasgupta wrote: > > > Thanks for reviewing this. I added a top comment for AddInsnClass > and I fixed the violation of column numbers. > > Great. Looks good to me. > >

Ivan, Thanks for working on the DFA generator. I'll take a look at the changes in detail but from your description, I like the general nature of the modifications. -Anshu --- Qualcomm Innovation Center, Inc is a member of the Code Aurora Forum On 6/14/2012 8:22 AM, Ivan Llopard wrote: > Hi, > > I've refactored the DFA generator in TableGen because it takes too > much