similar to: Is there a way to convert between SchedMachineModel and Itineraries?

----- Original Message ----- > From: "Rail Shafigulin via llvm-dev" <llvm-dev at lists.llvm.org> > To: "llvm-dev" <llvm-dev at lists.llvm.org> > Sent: Monday, November 9, 2015 10:09:07 AM > Subject: Re: [llvm-dev] Is there a way to convert between SchedMachineModel and Itineraries? > > > Anybody? Does anyone at all know how to do it? There is

> On Nov 9, 2015, at 10:49 AM, Rail Shafigulin <rail at esenciatech.com> wrote: > > On Mon, Nov 9, 2015 at 10:31 AM, Hal Finkel <hfinkel at anl.gov <mailto:hfinkel at anl.gov>> wrote: > ----- Original Message ----- > > From: "Rail Shafigulin via llvm-dev" <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> > > To:

I'm unclear how does DFAPacketizer and the scheduler know a given instruction is a load. Here is what I'm talking about Let's assume my VLIW target is described as follows: def MyTargetItineraries : ProcessorItineraries<[Slot0, Slot1], [], [ .............................. InstrItinData<RI, [InstrStage<1, [Slot0, Slot1]>]>,

Hi Phil. You more or less answered your own question, but let me give you some more info. Maybe it is of use. >From what I understand the SchedMachineModel is the future, although it is not as powerful as itineraries at present. The mi-scheduler is mostly developed around out-of-orders cores, I believe (I love to hear arguments on the contrary). Some of the constraints that can be found in

So if I use the SchedMachineModel method, can I just skip itineraries? Phil On Wed, Apr 20, 2016 at 12:29 PM, Sergei Larin <slarin at codeaurora.org> wrote: > Target does make a difference. VLIW needs more hand-holding. For what you > are describing it should be fairly simple. > > > > Best strategy – see what other targets do. ARM might be a good start for > generic

On Apr 26, 2013, at 3:53 AM, Martin J. O'Riordan <Martin.ORiordan at movidius.com> wrote: > I am migrating the llvm/clang derived compiler for our processor from the > v3.1 to v3.2 codebase. This has mostly gone well except that instruction > latency scheduling is no longer happening. > > The people who implemented this previously sub-classed 'ScheduleDAGInstrs'

It it possible to specify an instruction latency in the itinerary through a command line option? We have several options for a hardware divider which have different latencies and it would be nice if I could specify it through a compiler option rather than changing the value in the code and recompiling llvm every time? Any help is appreciated. -- Rail Shafigulin Software Engineer Esencia

Hi everyone I'm fairly new with LLVM and I've been searching around but couldn't find info on this subject. I started working on a target for a new cpu and I realizing my initial simple understanding of instruction itineraries may be completely off. I'm trying to model a CPU that has a latency of 2 cycles for multiplications fully pipelined (so it can start a new one after one

I'm trying to enable/disable a target feature through clang. Here is how my target looks like // Esencia subtarget features //===----------------------------------------------------------------------===// def FeatureMul : SubtargetFeature<"mul", "HasMul", "true", "Enable hardware multiplier">; def FeatureDiv

Hi, I am extending LLVM for HPC applications. As one of them, I am trying to make MachinePipeliner available on AArch64 + Scalable Vector Extension environment. MachinePipeliner is currently used only by Hexagon CPU. Since it is a very portable implementation, I think that it will actually work just by adding a little code for many CPUs(See Code [2]). The current MachinePipeliner is written on

On Mon, Aug 15, 2011 at 4:03 PM, Miguel G <miguel at esenciatech.com> wrote: > Hi everyone > I'm fairly new with LLVM and I've been searching around but couldn't find > info on this subject. > I started working on a target for a new cpu and I realizing my initial > simple understanding of instruction itineraries may be completely off. > I'm trying to model a

> > No, this would have to be a void side effecting instruction which is a bit > different. What do you mean by "void side effecting instruction"? I'm not sure I fully understand what you mean. The flag register is an implicit register added to the selected > MachineInstr's operands. Is this something that is always done by LLVM? Is it me who is telling to LLVM

Dear Andrew and the Group, I’m trying come up with a SchedMachineModel for the AMD bulldozer http://en.wikipedia.org/wiki/Bulldozer_(microarchitecture). The model is not exist for the same .Please correct me if am i wrong here. I was going through your reference @ https://llvm.org/svn/llvm-project/llvm/trunk/include/llvm/Target/TargetSchedule.td . But I couldn’t model some of the

> Does the instruction that is being added have an itinerary associated with > it? > So I checked again, and it turns out that it does have an itinerary associated with it. However it is a pseudo instruction. Does the packetizer do something special with the pseudo instructions? I didn't see any special code, but I could have missed it. -- R -------------- next part --------------

Dear All, Attached files is related to the changes made to add the Schedmodel for a AMD bulldozer target, Please note that , the model is incomplete but has some of the valuables features implemented. Request to the group or someone from AMD for the comments on the implementation. Thanks ~umesh On Wed, Nov 13, 2013 at 8:14 PM, Umesh Kalappa <umesh.kalappa0 at gmail.com>wrote: >

> In particular, the LoadLatency is used in defaultDefLatency: > > /// Return the default expected latency for a def based on it's opcode. > unsigned TargetInstrInfo::defaultDefLatency( > const MCSchedModel &SchedModel, const MachineInstr *DefMI) const { > if (DefMI->isTransient()) > return 0; > if (DefMI->mayLoad()) > return

Kun, Thanks for the reply. I looked at it, but wasn't able to find where actual instruction bundling takes place, i.e. where exactly in the code they pack instruction into a single bundle. Do you know where it is done? I would really appreciate any pointers. Thanks. On Fri, Sep 25, 2015 at 4:37 PM, Kun Ling <kunling at lingcc.com> wrote: > Hi Rail, > For the VLIW support,

On Tue, Nov 17, 2015 at 11:15 AM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > On 11/17/2015 12:26 PM, Rail Shafigulin wrote: > >> >> I tried setting >> let mayLoad = 1 { >> class InstrLD .... { >> } >> } >> >> But that didn't seem to work. When I looked at the debug output the >> latency for the load

On Thu, Mar 17, 2016 at 2:41 PM, Rail Shafigulin <rail at esenciatech.com> wrote: > On Thu, Mar 17, 2016 at 10:10 AM, Rail Shafigulin <rail at esenciatech.com> > wrote: > >> On Wed, Mar 16, 2016 at 6:38 PM, Mehdi Amini <mehdi.amini at apple.com> >> wrote: >> >>> >>> On Mar 16, 2016, at 5:38 PM, Rail Shafigulin <rail at

Thanks Eli. Somehow I was assuming the scheduler would insert NOPs to enforce latencies The CPU I'm dealing with doesn't automatically stall, i.e. latency must be ensured by the program. As an alternative to a pass, is it feasible to modify the scheduler to do so (optionally) or it would be too complicated. If possible, what would be the right place to look ? Thanks so much Miguel On