similar to: Instructions with no operand

On 11/6/2015 11:35 AM, Sky Flyer via llvm-dev wrote: > Guys, I stuck at this point. Could you please give me a hint how to > solve this problem without touching the LLVM backbone?! > Why LLVM doesn't let me define an instruction consisting of an operator > with no operand? Could you try it without the pattern? I.e. just this: class TestInst<string opc, string asmstr,

On Jan 9, 2007, at 5:23 PM, Scott Michel wrote: > Chris Lattner wrote: >>> It is possible to write multi-instruction pattern, e.g. >>> X86InstrSSE.td line 1911. But how are you defining HI16 and LO16? >>> Sounds like you want to define them as SDNodeXform that returns >>> upper >>> and lower 16 bits respectively. Take a look at PSxLDQ_imm in

Chris Lattner wrote: >>It is possible to write multi-instruction pattern, e.g. >>X86InstrSSE.td line 1911. But how are you defining HI16 and LO16? >>Sounds like you want to define them as SDNodeXform that returns upper >>and lower 16 bits respectively. Take a look at PSxLDQ_imm in >>X86InstrSSE.td as an example. > > > Another good example is the PPC

On Tue, 9 Jan 2007, Evan Cheng wrote: >> - How does one deal with multiple instruction sequences in a pattern? >> To load a constant is a two instruction sequence, but both >> instructions only take two operands (assume that r3 is a 32-bit >> register): >> >> ilhu $3, 45 # r3 = (45 << 16) >> iohl $3, 5 # r3 |= 5

Hi Andy and all, I have a question about per-operand machine model. I am finding some relations between 'MCWriteLatencyEntry' and 'MCWriteProcResEntry'. For example, class InstTEST<..., InstrItinClass itin> : Instruction { let Itinerary = Itin; } // I assume this MI writes 2 registers. def TESTINST : InstTEST<..., II_TEST> // schedule info II_TEST:

When I setup my InstrFormat fields, I added some custom fields specific for my backend. How do I access these from inside LLVM? For example: class InstrFormat<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { let Namespace = "AMD"; dag OutOperandList = outs; dag InOperandList = ins; let Pattern = pattern; let

Hi Daniel, Thanks for replying; I was hoping to get in touch with you on this issue. I had a look at how SelectionIDAG does it when generating the matcher table, and it does consider the implicit defs as additional output. Here is the match table generated for the pattern: /* 0*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND), /* 3*/ OPC_MoveChild0, /* 4*/ OPC_CheckOpcode,

Hi, I was compiling libc++ with a recent TOT (248571) and when I got to the ARMv6, I got a code generation error in memory.cpp: fatal error: error in backend: Cannot select: intrinsic %llvm.arm.clrex ecc: error: clang frontend command failed with exit code 70 (use -v to see invocation) clang version 3.8.0 (trunk) It looks as if the newly added emitAtomicCmpXchgNoStoreLLBalance() function is

On Thu, Apr 18, 2019 at 05:51:06PM +0200, Michal Prívozník wrote: > On 4/17/19 10:24 AM, Sachin Soman wrote: > > Hi, > > > > Could you tell me if the following is some known issue? > > > > While performing the following simple test, I see my JVM crashing > > (consistently): > > 1. Open a connection to an ESXi driver/host (passing ConnectAuthDefault

On Aug 1, 2012, at 1:53 PM, Jyotsna Verma <jverma at codeaurora.org> wrote: > > Currently, we rely on switch tables to transform between formats. However, > we would like to have a different mechanism to represent these relationships > instead of switch tables. I am thinking of modeling these relations in > HexagonInstrInfo.td file and use TableGen to generate a table with

On Thu, Apr 18, 2019 at 10:46:19PM +0530, Sachin Soman wrote: > I am attaching the execution results. At the top of each file I have > mentioned the environment details. > > Following is the test program I have used: > > ================================================== > > *package* org.libvirt; > > > *import* org.libvirt.jna.Libvirt; > > >

Hi Everyone, After some more thoughts to the Jacob's suggestion of using multiclasses for Opcode mapping, this is what I have come up with. Please take a look at the design below and let me know if you have any suggestions/questions. I have tried to keep the design target independent so that other targets could benefit from it. 1) The idea is to add 3 new classes into

Dear all, I am trying to write an AsmParser and a CodeEmitter for simple ADD instruction. Here is what I have in the TestGenInstrInfo.td: *extern const MCInstrDesc TestInsts[] = {...{ 23, 3, 1, 0, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo13, 0, nullptr }, // Inst #23 = ADD8_rr...}* I parse the instruction successfully but I am not sure what I did wrong that the Size (as you can see in

On Fri, Sep 25, 2015 at 2:17 PM, JF Bastien <jfb at google.com> wrote: > Looks like this was caused by r248294. Author CC'ed. > > On Fri, Sep 25, 2015 at 1:46 PM, Richard Pennington via llvm-dev > <llvm-dev at lists.llvm.org> wrote: >> >> Hi, >> >> I was compiling libc++ with a recent TOT (248571) and when I got to the >> ARMv6, I got a

Hi, I'm looking for some suggestions on a problem related to the Hexagon backend. Hexagon architecture allows instructions in various formats. For example, we have 3 variations of the add instruction as defined below: ADDrr : r1 = add(r2, r3) --> add 2 32-bit registers ADDrr_p : if(p0) r1 = add(r2, r3) --> predicated version of ADDrr instruction, executed when p0 is true ADDrr_np :

Currently the AtomicExpandPass will lower the following IR: define i1 @foo(i32* %obj, i32 %old, i32 %new) { entry: %v0 = cmpxchg weak volatile i32* %obj, i32 %old, i32 %new _*release acquire*_ %v1 = extractvalue { i32, i1 } %v0, 1 ret i1 %v1 } to the equivalent of the following on AArch64: _*ldxr w8, [x0]*_ cmp w8, w1 b.ne .LBB0_3 // BB#1:

Note: A couple of times I have seen errors while closing the connection (the trace ending with virFree). Also, a few times I have seen backtraces which show the flow going via esx driver and finally failing to close connection. Unfortunately I dont have those logs anymore. The execution results I have shared have been obtained using Libvirt built from source using the following config parameters:

Did you get a chance to debug the issue? Thanks & Regards, Sachin Soman On Thu, Apr 18, 2019, 11:10 PM Sachin Soman <sachonline.soman@gmail.com> wrote: > I have tried the same tests using the "test" driver, and that works > perfectly; no errors seen. > > Thanks & Regards > Sachin Soman > > > > > On Thu, Apr 18, 2019 at 11:03 PM Daniel P.

On Sep 23, 2011, at 1:38 PM, David A. Greene wrote: > Jakob Stoklund Olesen <stoklund at 2pi.dk> writes: > >> It appears that tablegen is inferring the 'type' of an individual >> register by enumerating all the register classes it appears in. Some >> things, like using implicit defs in SDNodes, only works for registers >> with a unique type. My

On OS X 10.5.5 I get an error that ld doesn't support -export-dynamic: dhcp-172-19-103-185:~/src/llvm/trunk_nolibtool/obj jyasskin$ ../src/configure --prefix=`pwd`/../install && make VERBOSE=1 ... dhcp-172-19-103-185:~/src/llvm/trunk_nolibtool/obj jyasskin$ make VERBOSE=1 for dir in lib/System lib/Support utils lib/VMCore lib tools/llvm-config tools docs; do \ if [ ! -f