similar to: Error compiling libc++ for ARMv6

On Fri, Sep 25, 2015 at 2:17 PM, JF Bastien <jfb at google.com> wrote: > Looks like this was caused by r248294. Author CC'ed. > > On Fri, Sep 25, 2015 at 1:46 PM, Richard Pennington via llvm-dev > <llvm-dev at lists.llvm.org> wrote: >> >> Hi, >> >> I was compiling libc++ with a recent TOT (248571) and when I got to the >> ARMv6, I got a

Hi, I have problem with IRBuilderBase::InsertPointGuard class that simply does not work in the release build of my project. The class does not restore the IRBuilder's insert point correctly when NDEBUG macro is set. It happens on OSX system only, trunk version of the LLVM built with brew. I suspect it is the ABI problem. InsertPointGuard uses AssertingVT for debug builds. LLDB gets confused

Hi all, consider the following function from Core.cpp in LLVM 9.0.0: LLVMValueRef LLVMBuildMalloc(LLVMBuilderRef B, LLVMTypeRef Ty, const char *Name) { Type* ITy = Type::getInt32Ty(unwrap(B)->GetInsertBlock()->getContext()); Constant* AllocSize = ConstantExpr::getSizeOf(unwrap(Ty)); AllocSize = ConstantExpr::getTruncOrBitCast(AllocSize, ITy);

This addition converts strlen() calls to strnlen() when the result is compared to a constant. For example, the following: strlen(s) < 5 Becomes: strnlen(s, 5) < 5 That way, we don't have to walk through the entire string. There is the added overhead of maintaining a counter when using strnlen(), but I thought I'd start with the general case. It may make sense to only use this

Hi, As a follow up to Patch D23646 <https://reviews.llvm.org/D23646>, I'm trying to figure out if there should be an alignment check and what the correct approach is. Some background: For stores, the pass turns: %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11> store <12 x i32> %i.vec, <12 x i32>* %ptr

On 11/6/2015 11:35 AM, Sky Flyer via llvm-dev wrote: > Guys, I stuck at this point. Could you please give me a hint how to > solve this problem without touching the LLVM backbone?! > Why LLVM doesn't let me define an instruction consisting of an operator > with no operand? Could you try it without the pattern? I.e. just this: class TestInst<string opc, string asmstr,

Hello, My code: (CallInst *CI, IRBuilder<> &B) SmallVector<Value *, 8> args; Value *v = B.CreateGlobalString("hi", "str"); args.push_back(v); SmallVector<Type*, 8> params; params.push_back(v->getType()); Module *M = B.GetInsertBlock()->getParent()->getParent(); FunctionType *printfType =

Hi all, I am trying to implement an instruction with no operand for example "clr" in TableGen. ----------------------------------------- e.g. *InstrInfo.td:* class TestInst<string opc, string asmstr, dag oops, dag iops, list<dag> pattern> : Instruction { ... } def int_no_operand : Intrinsic<[]>; class ALU<string opc> : TestInst<opc,

Currently the AtomicExpandPass will lower the following IR: define i1 @foo(i32* %obj, i32 %old, i32 %new) { entry: %v0 = cmpxchg weak volatile i32* %obj, i32 %old, i32 %new _*release acquire*_ %v1 = extractvalue { i32, i1 } %v0, 1 ret i1 %v1 } to the equivalent of the following on AArch64: _*ldxr w8, [x0]*_ cmp w8, w1 b.ne .LBB0_3 // BB#1:

On 15 September 2015 at 19:34, Daniel Sanders <Daniel.Sanders at imgtec.com> wrote: > We can go further with this analogy too. For example, let's say John Smith > with the SSN Y also answers to the name Rameses. This is the problem that > Renato is working on. Renato needs to be able to see the name Rameses and > map this to the correct John Smith (or at least someone very

On Sep 22, 2011, at 11:47 AM, Valentin Radu wrote: > checking for armv7-apple-darwin-clang... no > checking for armv7-apple-darwin-llvm-gcc... no > checking for armv7-apple-darwin-gcc... no It's because you don't have a compiler around that targets arm by default. -eric -------------- next part -------------- An HTML attachment was scrubbed... URL:

On Sep 22, 2011, at 11:51 AM, Eric Christopher wrote: > > On Sep 22, 2011, at 11:47 AM, Valentin Radu wrote: > >> checking for armv7-apple-darwin-clang... no >> checking for armv7-apple-darwin-llvm-gcc... no >> checking for armv7-apple-darwin-gcc... no > > It's because you don't have a compiler around that targets arm by default. Exactly right. You

On Fri, Sep 25, 2015 at 05:34:03PM -0700, JF Bastien via llvm-dev wrote: > In pre-v6 Linux you could use the kernel-provided helpers: > > https://www.kernel.org/doc/Documentation/arm/kernel_user_helpers.txt Please *never* tell people to use those directly. There are kernels other than Linux and the very idea of hardcoding random kernel address should make all red warning lights go off.

On Sun, Sep 27, 2015 at 05:07:17PM -0700, JF Bastien wrote: > It's part of the stable Linux ABI for ARM. Yes there are non-Linux OSes, > and I wasn't suggesting one emit these calls for non-Linux. > > Please clarify the red warning lights. FWIW these functions were used by > Chrome on ARM until very recently, specifically for the sake of older ARM > CPUs. I know. It is

Hello, I am trying to build a speex library file for armv6 on intel MAC OS. I've also put -enable-arm5e-asm whether arm5e-asm works or not. ./configure -prefix=/Users/mijin/temp -disable-shared -enable-static - enable-fixed-point -enable-arm5e-asm This gives below errors. gcc -DHAVE_CONFIG_H -I. -I. -I.. -I../include -I../include -I.. -g - O2 -fvisibility=hidden -MT cb_search.lo -MD

Hello, For the last couple of days I struggled to find a way to compile LLVM with Clang for ARM. Now, I tried many variations of the settings, linkers and compilers, but I was able only to build for i386 and x86_64. My machine is an i386 iMac. This is my first attempt to cross-compile something, so probably I'm doing something incredible stupid. First, I'm not sure which compiler should

Hi, all I want to use LLVM to compile an ARM Cortex-M0 project on windows. Who can send me a sample, including command arguments and introdution about debug process. Thanks a lot. -Steven ***************************** Legal Disclaimer ***************************** "This email may contain confidential and privileged material for the sole use of the intended recipient. Any unauthorized

# RFC: Atomic LL/SC loops in LLVM revisited ## Summary This proposal gives a brief overview of the challenges of lowering to LL/SC loops and details the approach I am taking for RISC-V. Beyond getting feedback on that work, my intention is to find consensus on moving other backends towards a similar approach and sharing common code where feasible. Scroll down to 'Questions' for a summary

Hi Renato, Thank you for the answers! First, let me clarify a couple of things and give some context. The patch it looking at VSTn, rather than VLDn (stores seem to be somewhat harder to get the "right" patterns, the pass is doing a good job for loads already) The examples you gave come mostly from loop vectorization, which, as I understand it, was the reason for adding the

2013/4/24 Alex L <arphaman at gmail.com> > You may want to check the later versions of the standard also to check if >> some of your proposal is not deprecated there. >> > I had a quick check with 2008 standard, and I'm pretty sure that all of > the stuff that I chose is there, although a lot of it has various additions > and changes. > The EQUIVALENCE