Displaying 20 results from an estimated 10000 matches similar to: "Working with X86 registers in MachineInstr"
2016 Feb 17
2
Getting MachineInstr opcode mnemonics as strings
Hello all,
Is there an easy way to get the human-readable opcode mnemonic (e.g.,
"MOV32ri64", "CMP32ri8", "JLE_1") for a MachineInstr? I am writing a
backend analysis pass for security research, where the idea is for a
researcher to examine the output of my pass and identify instructions
from it for use in an attack. Right now I'm representing unique
2015 Jul 02
2
[LLVMdev] Load MachineFunctionPass plugin from library in llc?
Hi all,
I am working on creating a MachineFunctionPass to perform an analysis on X86
code. After a bit of trouble, I was able to get my pass compiling and
running correctly in llc. However, since a machine pass is compiled directly
into the code generator, rerunning "make" across the LLVM build tree
involves re-linking most of the major libraries and executables. This is a
rather
2012 Oct 29
3
[LLVMdev] [llvm-commits] [llvm] r162770 - in /llvm/trunk: include/llvm/CodeGen/MachineOperand.h lib/CodeGen/MachineInstr.cpp
Jakob and anyone else who might be interested...
Base on this patch back in August, I sense some need to double check with
you whether it is OK to start making a heavy use of MachineOperand
TargetFlags?
We do seem to have a compelling reason for it in Hexagon, and I wanted to
make sure that it is OK with everyone. I plan to use it for attributing
target specific info to MOs and in more general
2012 Oct 29
0
[LLVMdev] [llvm-commits] [llvm] r162770 - in /llvm/trunk: include/llvm/CodeGen/MachineOperand.h lib/CodeGen/MachineInstr.cpp
Hi Sergei,
our use of target flags will be on immediate register operands if I am
not mistaken (and if not we can always encode it as such)?
I guess you are refering to the hexagon backend needing to distinguish
between instances of an instruction that uses a constant value that
can fit into the 4 byte of the instruction and one that encodes the
immediate in an extra instruction slot (what we
2016 Mar 21
1
[GSoC 2016] Adding MachineModule pass to LLVM
Hello Community,
I have submitted my draft proposal for this project on the summer of code
web site and shared it with the community. Please take a look at it and
suggest/ comment some modifications. I have already done some study on the
relevant code. I will still do some more before the final submission but
this is more of designing challenge please help !
Sincerely,
*Vivek Pandya*
2015 Jul 02
2
[LLVMdev] Load MachineFunctionPass plugin from library in llc?
> On Jul 2, 2015, at 2:05 PM, Jim Grosbach <grosbach at apple.com> wrote:
>
>>
>> On Jul 2, 2015, at 1:17 PM, Ethan J. Johnson <ejohns48 at cs.rochester.edu <mailto:ejohns48 at cs.rochester.edu>> wrote:
>>
>> Hi all,
>>
>> I am working on creating a MachineFunctionPass to perform an analysis on X86 code. After a bit of trouble, I was
2012 Oct 29
2
[LLVMdev] [llvm-commits] [llvm] r162770 - in /llvm/trunk: include/llvm/CodeGen/MachineOperand.h lib/CodeGen/MachineInstr.cpp
Arnold,
I wanted to hear from Jacob is the original patch in question still needed,
since our use of this field could surpass const extenders and could
potentially include MO_Register.
Jacob,
Can you please comment? Thanks.
Sergei
---
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
The Linux Foundation
> -----Original Message-----
> From: Arnold
2010 Jan 15
0
[LLVMdev] <IsKill> getting from MachineOperand is just <Used> attribute from logic.
On Jan 14, 2010, at 6:39 PM, 任坤 wrote:
> But I want do some optimization after register alloction by adjusting
> register using. I scan MachineBasicBlock to analyze operand's IsKill, IsDead , IsDef attribute to get a physical register's liverange. But I get a strange case at MBB.jpg.
You can also look at RegisterScavenging.cpp and MachineVerifier.cpp. They are doing the same
2010 Jan 15
2
[LLVMdev] <IsKill> getting from MachineOperand is just <Used> attribute from logic.
Hi,
I have ported LLC to a risc cpu. It can pass benchmark that I have at current.
But I want do some optimization after register alloction by adjusting
register using. I scan MachineBasicBlock to analyze operand's IsKill, IsDead , IsDef attribute to get a physical register's liverange. But I get a strange case at MBB.jpg.
R4 is marked <kill> at MBB0. If I scan R4's
2015 Feb 11
2
[LLVMdev] deleting or replacing a MachineInst
This seems a very natural approach but I probably am having a trouble with
the iterator invalidation. However, looking at other peephole optimizers
passes, I couldn't see how to do this:
#define BUILD_INS(opcode, new_reg, i) \
BuildMI(*MBB, MBBI, MBBI->getDebugLoc(), TII->get(X86::opcode)) \
.addReg(X86::new_reg, kill).addImm(i)
for
2017 Aug 22
5
[RFC] mir-canon: A new tool for canonicalizing MIR for cleaner diffing.
Patch for review.
On Mon, Aug 21, 2017 at 11:45 PM Puyan Lotfi <puyan.lotfi.llvm at gmail.com>
wrote:
> Ping.
>
> Still working on preparing code for review. Will have a patch for review
> ready in the coming days.
>
> PL
>
> On Tue, Aug 15, 2017 at 12:06 PM Puyan Lotfi <puyan.lotfi.llvm at gmail.com>
> wrote:
>
>> Hi,
>>
>>
>>
2019 Mar 11
3
IsDead, IsKill
Thanks.
I saw the header comments but it wasn’t clear to me what the difference between those concepts is?
My slightly vague understanding is IsDef means that the register specified by this operand is set by the machine instruction. So I understand that to mean the MO will override that register?
Also things like early clobber, perhaps there is another document that clarifies some of these
2019 Mar 11
2
IsDead, IsKill
Is there anything that documents what these properties (and the other similar properties) do on the MachineOperand class?
I’m trying to debug an instruction selection issue I think. It’s hard to find documentation on what the MO properties mean.
Thanks,
Carl
2012 Sep 18
0
[LLVMdev] liveness assertion problem in llc
On Sep 18, 2012, at 1:45 PM, Bjorn De Sutter <bjorn.desutter at elis.ugent.be> wrote:
> I am working on a backend for a CGRA architecture with advanced predicate support (as on EPIC machines and as first used in the OpenIMPACT compiler). Until last month, the backend was working fine, but since the r161643 commit by stoklund, my backend doesn't work anymore. I think I noticed some
2012 Sep 18
2
[LLVMdev] liveness assertion problem in llc
Hi,
I am working on a backend for a CGRA architecture with advanced predicate support (as on EPIC machines and as first used in the OpenIMPACT compiler). Until last month, the backend was working fine, but since the r161643 commit by stoklund, my backend doesn't work anymore. I think I noticed some related commits later on, and the assertion I get on the latest trunk (r164162) differs from
2010 Aug 29
1
[LLVMdev] [Query] Programming Register Allocation
Thanks for the information.
I still don't know how do I partition registers into different classes from
the virtual registers? For instance, I have the function who which iterates
over the instructions, but I don't know how to write the function which
returns the different register class.
void RAOptimal::Gather(MachineFunction &Fn) {
// Gather just iterates over the blocks,
2015 Apr 28
2
[LLVMdev] RFC: Machine Level IR text-based serialization format
To get this out first: I'd love to have a way to serialize machine-IR! I often spend a lot of time trying to create .ll files in a way that the machine-IR still looks a certain way when it finally hits the relevant passes in codegen. It would be so much easier to just specify the machine IR immediately before the pass I'm interested in.
For that use case it is worth keeping the following
2005 Sep 07
4
[LLVMdev] LiveIntervals, replace register with representative register?
I don't understand the following code snippet in LiveIntervalAnalysis.cpp.
Why changing the type of the opreand from a virtual register to a
machine register? The register number (reg) is still a virtual
register index (>1024).
bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
// perform a final pass over the instructions and compute spill
// weights, coalesce
2015 Feb 11
2
[LLVMdev] deleting or replacing a MachineInst
I'm writing a peephole pass and I'm done with the X86_64 instruction level
detail work. But I'm having difficulty with the basic block surgery
of replacing the old MachineInst.
The peephole pass gets called per MachineFunction and then iterates over
each MachineBasicBlock and in turn over each MachineInst. When it finds an
instruction which should be replaced, it builds a new
2016 Jul 28
2
Liveness of virtual registers
Dear there,
I am trying to use liveness of a variable while writing a machinefunction
pass. But it seems that some virtual registers are not marked as dead while
they should be (never used by anything else). I get those info by callings
isDead or isDef function for that MachineOperand (vreg). Is there a way to
get more accurate liveness info?
Thanks,
Xiaochu
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