similar to: [LLVMdev] RFC: what is the purpose of test/CodeGen/Generic?

I checked recent revisions 138624 and 138620 and both produce this log with gcc-4.6.0 on FreeBSD-8.2-STABLE amd64: gmake[2]: Entering directory `/usr/home/yuri/llvm-svn/llvm-objects/lib/CodeGen' llvm[2]: Compiling LLVMTargetMachine.cpp for Release build /usr/home/yuri/llvm-svn/llvm/lib/CodeGen/LLVMTargetMachine.cpp:253:3: error: ‘AsmStreamer’ does not name a type

> -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of Tom Stellard > Sent: 19 September 2014 01:36 > To: Sanjay Patel > Cc: llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] predicates vs. requirements [TableGen, > X86InstrInfo.td] > > On Thu, Sep 18, 2014 at 03:25:07PM -0600, Sanjay Patel wrote: >

I am trying to understand how LLVM does code generation and I have a couple of questions. I am using LLVM 2.6. First, if I want to change the name of an instruction, all I need to do is to modify the XXXInstrInfo.td, right? Using Sparc as an example, if I wanted to output "mysra" instead of "sra", in SparcInstrInfo.td, I would write, defm SRA : F3_12<"mysra",

>>> The Hexagon precedent is interesting; Krzysztof said they set the default >>> triple, and didn't have to xfail all that much stuff. Searching the tree, >>> I find exactly 7 individual tests marked XFAIL: hexagon, plus it disables >>> all of ExecutionEngine, and turns off the 'object-emission' feature. >>> >>> I'm curious

Hi all, I can't find a way to add a MachineFunctionPass to the common codegen passes (LLVMTargetMachine::addPassesToEmitMachineCode) while JITting (the pass manager is associated with the jitstate of the JIT and I can't access it because it's private). Have I missed something? Or adding a MachineFunctionPass to codegen requires to change the

On 1/20/11 12:27 PM, Venkatraman Govindaraju wrote: Just out of curiosity, have either of you considered writing an LLVM transform that simply replaces these call instructions with inline assembly code that does what you want? If that works, it seems much simpler than modifying/enhancing the code generator. -- John T. > I have similar requirements for my project. This is what I do. >

Hello all, I am trying to modify the Sparc backend to do something for my team's project, to do the following. Whenever the backend encounters a call to one particular type of function names (functions like p0(), p1()..etc), I want the backend to generate a "sethi %g0, <number>", and NOT a "call p0, call p1..." instruction. However, the backend should work as usual

For my case, I can't replace these call instructions with inline assembly code because I need to encode the registers into the "number". For instance, if the call instruction is %result = call i32 @foo(i32 %a) and the result is assigned to register %l0 and the variable "a" to register %l1, then I encode all foo, %l0 and %l1 and generate a sethi instruction. thanks,

Hi all, *TL;DR:* I have a target TMS9900CodeGen but cmake is looking for LLVMTMS9900 or LLVMTMS9900CodeGen which I don't have, and cmake dies. But the MSP430 target doesn't have that either, and cmake is happy with it. What am I missing? *The premise:* I may be making a huge mistake, but I'm trying to develop an LLVM backend. I'm writing up some notes while I do so, and I hope

I have similar requirements for my project. This is what I do. 1. Add a new intrinsic function to LLVM that corresponds to "functions with particular type of function names". The steps to create intrinsic function is documented in http://llvm.org/docs/ExtendingLLVM.html#intrinsic. 2. Create a lowering pass that lowers "functions with particular type" ( eg. p0, p1) to

Has anybody used the Pattern class. We all use Pat and ComplexPattern but I can't find any examples of Pattern. I have some instructions that I'm currently treating as pseudos but I'd like to treat them as patterns with several instructions but this does not seem to work, at least I can't get it to work so far. I get an error: Cannot handle instructions with temporaries yet!

I'm trying to define a multiply-accumulate instruction for the LEON processor, a Subtarget of the Sparc target. The documentation for the processor is as follows: === To accelerate DSP algorithms, two multiply&accumulate instructions are implemented: UMAC and SMAC. The UMAC performs an unsigned 16-bit multiply, producing a 32-bit result, and adds the result to a 40-bit accumulator made

Hello, When I run LLC with option "-O0 -march=sparc" on following testcase, fast register allocator crashes with "UNREACHABLE executed" error. LLC generates code successfully with other standard register allocators available. $ cat call.ll define void @test() nounwind { entry: %0 = tail call i32 (...)* @foo() nounwind tail call void (...)* @bar() nounwind ret void }

Hi I am new to llvm and Linux (I am using ubuntu 10) My aim is to add backend to llvm. I install llvm using $ sudo apt-get install llvm and I am able to understand what I read about Writing an LLVM Compiler Backend. I have seen the assembly codes of the targets on llvm using llc. What I need now is to change some of the TableGen files of one of the target like SparcInstrInfo.td.  So I

> On May 27, 2015, at 2:18 PM, Duncan P. N. Exon Smith <dexonsmith at apple.com> wrote: > > >> On 2015 May 27, at 14:01, Alex L <arphaman at gmail.com> wrote: >> >> >> >> 2015-05-27 10:59 GMT-07:00 Duncan P. N. Exon Smith <dexonsmith at apple.com>: >>> On 2015 May 27, at 10:24, Chandler Carruth <chandlerc at google.com>

On Jan 1, 2010, at 12:51 PM, mmms1841 wrote: > I am trying to understand how LLVM does code generation and I have a couple of questions. > I am using LLVM 2.6. > > First, > if I want to change the name of an instruction, all I need to do is to modify the XXXInstrInfo.td, right? > Using Sparc as an example, if I wanted to output "mysra" instead of "sra",

On 09/04/2015 10:25 AM, Robinson, Paul via llvm-dev wrote: > >> -----Original Message----- >> From: James Y Knight [mailto:jyknight at google.com] >> Sent: Friday, September 04, 2015 10:12 AM >> To: Mehdi Amini; Mehdi Amini via llvm-dev >> Cc: Robinson, Paul >> Subject: Re: [llvm-dev] Testing "normal" cross-compilers versus GPU >> backends

Thanks for your last reply. Could I understand the way to adding a pass (built into the llvm rather than dynamic loadable) includes: 1. Declaring a creator function for this pass 2. Implementing the creator function for this pass 3. Instantiating this pass and get a object of it 3. Register this pass into the PassRegistry Then, for a built-into bytecode pass, task 1(declaration of the

Anton Korobeynikov wrote: > The patch is incorrect and the problems you're seeing are caused by > your patch, since sparc != sparc64. > In LLVM sense "sparc" means "sparc with ILP32 architecture model", > llvm does not support anything 64 bit in sparc world SparcTargetMachine.h file lists SparcV9TargetMachine as 64-bit machine and SparcV8TargetMachine as

You might want to refer to lib/Target/Sparc/SparcInstrInfo.td for examples of both Pat and ComplexPattern. Regards. 2012/9/16 Kotler, Reed <rkotler at mips.com>: > Has anybody used the Pattern class. We all use Pat and ComplexPattern but I > can't find any examples of Pattern. > > I have some instructions that I'm currently treating as pseudos but I'd like > to