similar to: [LLVMdev] between r241513 and r241594, clang 3.7.0svn now crashes building clang-tools-extra

Dear Community, The ponyc<https://github.com/CausalityLtd/ponyc/tree/llvm37> (llvm37 branch) project is facing an issue on Windows: When optimizations are turned on (llvm 3.7.0-final and more specifically<https://github.com/CausalityLtd/ponyc/blob/llvm37/src/libponyc/codegen/genopt.cc>, opt-level 3, BBVectorize, LoopVectorize, SLPVectorize, RerollLoops, LoadCombine + a custom heap

This got me into thinking. Indeed the problem is related to Windows exceptions, so I am not sure whether the bug reported<https://llvm.org/bugs/show_bug.cgi?id=24374> is actually fixed. Compiling Pony code (helloworld) that includes no exceptions does work fine (with optimizations). As soon as exceptions on windows come into play, writing the object file dies with the mentioned error in

… Also, it doesn’t appear that you are running on windows… From: David Majnemer Date: Saturday 12 September 2015 18:31 To: Sebastian Blessing Cc: Reid Kleckner, "llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>" Subject: Re: [llvm-dev] Optimizer issues on Windows $ ~/llvm/Debug+Asserts/bin/llc try.ll $ echo $? 0 On Sat, Sep 12, 2015 at 6:39 AM, Sebastian Blessing

Tobias, The most recent commits at svn revision 240868 have broken the Polly build on x86_64 on darwin... [ 57%] Building C object tools/polly/lib/CMakeFiles/Polly.dir/External/isl/isl_int_sioimath.c.o /sw/src/fink.build/llvm37-3.7.0-100/llvm-3.7.0.src/tools/polly/lib/External/isl/isl_int_sioimath.c:1:10: fatal error: 'malloc.h' file not found #include <malloc.h> ^ 1

Hi, I am wondering if anyone could run ArrayBoundChecks located in SafeCode-llvm37 (https://github.com/jtcriswell/safecode-llvm37) on llvm-3.8? Thanks. Syed -- Rafi

I'm getting this build error with -Werror: [off-opt] : [llvm] cc1plus: warnings being treated as errors [off-opt] : [llvm] /ptmp/dag/llvm/official/llvm/lib/Target/ARM/ARMISelLowering.cpp: In member function 'llvm::MachineBasicBlock* llvm::ARMTargetLowering::EmitAtomicBinary64(llvm::MachineInstr*, llvm::MachineBasicBlock*, unsigned int, unsigned int, bool, bool) const': [off-opt]

On 12 November 2010 17:52, Bob Wilson <bob.wilson at apple.com> wrote: > I recommend implementing this as a target-specific DAG combine optimization.  We already have target-specific DAG nodes for the relevant NEON comparison operations (ARMISD::VCEQ, etc. -- see ARMISelLowering.h) as well as the vmov (ARMISD::VMOVIMM).  You just need to teach the DAG combiner how to fold them together.

Is this related to Owen's patch r118453? Evan On Nov 12, 2010, at 10:42 AM, Renato Golin wrote: > On 12 November 2010 17:52, Bob Wilson <bob.wilson at apple.com> wrote: >> I recommend implementing this as a target-specific DAG combine optimization. We already have target-specific DAG nodes for the relevant NEON comparison operations (ARMISD::VCEQ, etc. -- see

On Nov 12, 2010, at 7:23 AM, Renato Golin wrote: > Hi folks, me again, > > So, I want to implement a simple optimization in a NEON case I've seen > these days, most as a matter of exercise, but it also simplifies (just > a bit) the code generated. > > The case is simple: > > uint32x2_t x, res; > res = vceq_u32(x, vcreate_u32(0)); > > This

On 10/27/16 11:18 AM, Aliaksei Zasenka via llvm-dev wrote: > Hi all, > Can anyone give me advice about an appropriate way for extracting > number of functions from module recursively (starting from entry > point). Actually it may be more than one entry point so all dependent > functions and global values must be extracted. > > I've tried llvm-extract tool but it

John, I've moved with patches to HEAD and unfortunately the comments about disabling tailcalls do not go away with this update. Please see ARMTargetLowering::LowerCall in lib/Target/ARM/ARMISelLowering.cpp line 1208 and later. It looks like man can use -arm-tail-calls, but one never knows how good it is since the comment tells it clearly: // Temporarily disable tail calls so things

Tobias, I can confirm that deleting the... #include <malloc.h> from the top of lib/External/isl/isl_int_sioimath.c allows the polly cmake build to complete on x86_64 darwin. Jack On Sat, Jun 27, 2015 at 2:25 AM, Tobias Grosser <tobias at grosser.es> wrote: > On 06/27/2015 03:39 AM, Jack Howarth wrote: >> >> Tobias, >> The most recent

Hi, all I am studying the ARM backend on SelectionDAG, I have some following questions: 1. Each operator of SDNode in SelectionDAG is required to be defined by SDNode<ISD::XXX,XXX,XXX> in .td file, right? But several operators are not defined in .td file, why? (e.g., ISD::BR_CC, ISD::CopyToReg, ISD::AssertSext) 2. The MVT::glue value is used to ensure two nodes are scheduled

I get the following error during compilation using the LLVM cross-compiler (x86_64->arm). error: nested functions are disabled, use -fnested-functions to re-enable With -fnested-functions switch, I get the following error: <llvm-src-dir>/llvm/lib/Target/ARM/ARMISelLowering.cpp:1439: virtual llvm::SDValue llvm::ARMTargetLowering::LowerOperation(llvm::SDValue, llvm::SelectionDAG&):

Hi, I'd like to make code emitted by LLVM that includes floating point operations which raise FP exceptions behave closer to what is defined by IEEE754 standard. I'm not going to "fix everything", just incorrect behaviour I faced so far. Most of troubles regarding FP exceptions are caused by optimizations, so there should be a flag to disable/block them if one wants to get

Hi Jonas, There's not really a very clean way to do this currently. The ARM backend does it as you indicate with the writeback register listed as an output as well as an input and marked as a tied operand constraint. Search for _PRE and _POST in ARMInstrInfo.td for examples. For most instances, instruction selection is done via custom lowering, not an ISel pattern on the pattern; see

I have been struggling with this for way too long now, so hopefully the mighty list can help: I am trying to generate a byte store instruction storing the constant value 4 at some given address in a new helper function inside ARMISelLowering.cpp I tried: SDValue Val = DAG.getConstant(4, MVT::i8); SDValue Store = DAG.getStore(chain, dl,

Hi, Looking at bugzilla PR11087, I'd like to conditionalise a transformation in ARMIselLowering.cpp based on whether we're compiling for codesize or performance. -Os doesn't actually exist for llc, and I can't see an obvious place where that condition would be set. Where do we specify if we're optimizing for codesize or performance? Cheers, James --------------

On Mon, Oct 17, 2011 at 7:58 AM, James Molloy <james.molloy at arm.com> wrote: > Hi, > > > > Looking at bugzilla PR11087, I’d like to conditionalise a transformation in > ARMIselLowering.cpp based on whether we’re compiling for codesize or > performance. > > > > -Os doesn’t actually exist for llc, and I can’t see an obvious place where > that condition

On 28 July 2015 at 17:52, Sumanth Gundapaneni <sgundapa at codeaurora.org> wrote: > Android bionic libc doesn’t provide a __modsi3, instead it provides > “__aeabi_idivmod”. Hi Sumanth, Have a look at ARMSubtarget.h, functions: bool isTargetAEABI() They control the lowering of DIV/MOD calls in ARMISelLowering.cpp. Maybe Android needs to be in? cheers, --renato