similar to: [LLVMdev] Load MachineFunctionPass plugin from library in llc?

> On Jul 2, 2015, at 2:05 PM, Jim Grosbach <grosbach at apple.com> wrote: > >> >> On Jul 2, 2015, at 1:17 PM, Ethan J. Johnson <ejohns48 at cs.rochester.edu <mailto:ejohns48 at cs.rochester.edu>> wrote: >> >> Hi all, >> >> I am working on creating a MachineFunctionPass to perform an analysis on X86 code. After a bit of trouble, I was

Hi all, I am attempting to implement the "reaching definitions" data-flow algorithm on (X86) MachineBasicBlocks for an analysis pass. To do this, I need to compute gen/kill sets for machine basic blocks. To start with, I am only considering the general-purpose registers, RAX-R15 and their sub-registers. Thus, I need to examine each MachineInstr to determine which register(s) it

Hello all, Is there an easy way to get the human-readable opcode mnemonic (e.g., "MOV32ri64", "CMP32ri8", "JLE_1") for a MachineInstr? I am writing a backend analysis pass for security research, where the idea is for a researcher to examine the output of my pass and identify instructions from it for use in an attack. Right now I'm representing unique

Hello Community, I have submitted my draft proposal for this project on the summer of code web site and shared it with the community. Please take a look at it and suggest/ comment some modifications. I have already done some study on the relevant code. I will still do some more before the final submission but this is more of designing challenge please help ! Sincerely, *Vivek Pandya*

Dear All, Is there a way in newer versions of LLVM (4.0 and higher) to find the size of an x86 instruction within a MachineFunctionPass?  If not, is there something I can do in the MC layer to do this? I'm trying to modify LLVM to implement something like Native Client in which groups of instructions are aligned at a specific alignment and have the same length.  My current approach is to

The actual size of even a MC instruction will change during relaxation--we don't choose between 8-bit jumps and wider jumps until relaxation. You can get the actual encoding of an MCInst via MCCodeEmitter, but if you expect relaxation to occur, or particularly if you're testing before register allocation, the size could only be an estimate and shouldn't be trusted for exact size.

Hello, I am writing a MachineFunctionPass that inspects the generated machine code, and examines each opcode and its corresponding operands. If the 'instruction + operands' match a particular sequence, then the pass should replace them with a fixed instruction + operands sequence. I tried using MachineInstr's getOpcode and getOperand functions but the pass didn't work as expected.

Hello , I have written a very simple MachineFunction Pass that currently does nothing. It compiles fine but when I try to load it with llc it give me following error: llc -optimize-regalloc=0 -load lib/GCRA.dylib -regalloc=gc test/fibo.bc Pass 'Bundle Machine CFG Edges' is not initialized. Verify if there is a pass dependency cycle. What is going wrong here ? Here is my very simple

Respected Dr. Criswell, My problem is that the output of following code looks nothing like any opcode: *for(MachineBasicBlock::iterator I = BB->begin(); I != BB->end(); ) { MachineInstr *mi = I; int op = mi->getOpcode(); std::cout << op << '\t'; }* I need to identify specific instructions in my MachineFunctionPass and I was hoping that I can

On 3/18/16 12:33 PM, Quentin Colombet via llvm-dev wrote: > Hi Vivek, > >> On Mar 16, 2016, at 1:00 PM, vivek pandya via llvm-dev >> <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: >> >> Hello, >> >> Probably this may be too late to start thinking about this project >> but I think this is particularly useful

Dear John, Thank you so much for your help. I looked at those documents. Could you kindly answer the following questions: Does it mean that I have to make my own backend target in order to write a machine pass even if I want to run a simple machinefunction pass? for example,if I want my pass to get MIPS instructions as an input, I have to copy all the files from mips target and add a file to it

Hi, Is there any way to detect which virtual registers are assigned to physical registers and which ones are assigned to memory slots? BR Laura -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160218/fb9b7659/attachment.html>

Hi, So, I run my pass in X86 target with llc command and it printed out "hello****". Now I am trying to do the same pass for ARM target. So I did exactly what I did for X86 as mentioned in my previous posts. When I run the following command: llc -march=arm test.ll -o test nothing prints out. I did the same for MIPS target too and I got no result. Can anyone tell me what I'm doing

Hi everyone, I am a LLVM newbie. I need to write a machinefunction pass for my project. This should be an analyzer of the machine code to do some profiling. I have written a couple of function passes for front end, but it seems they are completely different. I searched through forum and llvm documents, but couldn't find anything useful or questions were unanswered. Can anyone reference me to

Yes, I have done exactly the same. The wawanalyzer is the same. I changed ARM.h and ARMTargetMachine.cpp in the tager/arm folder. then I make tool/llc and lib folder. On Tue, Nov 17, 2015 at 10:55 AM, John Criswell <jtcriswel at gmail.com> wrote: > On 11/17/15 12:16 AM, fateme Hoseini via llvm-dev wrote: > > Hi, > So, I run my pass in X86 target with llc command and it printed

I'd like to generate an indirect call instruction that will end up as a call via memory and not register. The address of the target is a constant. For example, something like %25 = load i64, i64* @get_Now %26 = inttoptr i64 %25 to i64 ()* %27 = call i64 %26() may end up as mov rsi,qword ptr [00007FF658381070] call rsi or as call qword ptr [00007FF658381070] If I want to

Thank you so much. That helped alot. Fami On Wed, Nov 4, 2015 at 9:40 AM, John Criswell <jtcriswel at gmail.com> wrote: > On 11/3/15 7:54 PM, fateme Hoseini wrote: > > Dear John, > Thank you so much for your help. I looked at those documents. Could you > kindly answer the following questions: > > Does it mean that I have to make my own backend target in order to write

Deer All, I wanted to write MachineFunctionPass which needs to be run after global register allocation pass. I have read LLVM documentation and blogs and able to write simple pass which will is invoked through opt command line. However, I could able to find any blogs or document to explains clear steps for writing MachineFunctionPass. Please suggest some documents or blogs which will help me

Antony, What are you trying to accomplish in this case? I did something very similar in the AMDIL backend, but it was not the cleanest solution and you are correct it has to be do at doInitialization stage and not at runOnMachineFunction. Micah > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of Antony Yu > Sent:

First you should learn how to write a pass and then a MachineFunctionPass. >From LLVM website, you can refer to http://llvm.org/docs/WritingAnLLVMPass.html And for outside pass, you can refer to http://adriansampson.net/blog/llvm.html It's a great article. And the author put the source code on Github <https://github.com/sampsyo/llvm-pass-skeleton>. 2016-03-01 14:36 GMT+08:00