similar to: [LLVMdev] Supporting heterogeneous computing in llvm.

Christos, We would be very interested in learning more about this. In my group, we (Prakalp Srivastava, Maria Kotsifakou and I) have been working on LLVM extensions to make it easier to target a wide range of accelerators in a heterogeneous mobile device, such as Qualcomm's Snapdragon and other APUs. Our approach has been to (a) add better abstractions of parallelism to the LLVM instruction

Chirs, Have you seen an offloading infrastructure design proposal at http://lists.cs.uiuc.edu/pipermail/llvmdev/2015-April/084986.html ? It relies on the long-standing OpenMP standard with recent updates to support the heterogenous computations. Could you please review it and comment on how it fits to your needs? It's not quite clear from your proposal what source language standard do you

Hello, As I first e-mailed yesterday, I have been working on a Heterogeneous Execution Engine (Hexe) that provides compiler and runtime support for the automatic and transparent offloading of loop and function workloads to accelerators. Hexe is composed of the following: a) Analysis and Transformation Passes for extracting loops or functions for offloading. b) A runtime library that handles

Roel, You have to checkout and build llvm/clang as usual. For runtime support you'll have to build the libomptarget and make a plugin for your target. Samuel can help you some more. As for the OpenMP examples I can recommend you the http://openmp.org/mp-documents/OpenMP4.0.0.Examples.pdf look into the target constructs. Sergos On Mon, Jun 8, 2015 at 6:13 PM, Roel Jordans <r.jordans at

On Sun, Jun 7, 2015 at 2:22 AM, Eric Christopher <echristo at gmail.com> wrote: > > > On Sat, Jun 6, 2015 at 5:02 AM C Bergström <cbergstrom at pathscale.com> wrote: >> >> On Sat, Jun 6, 2015 at 6:24 PM, Christos Margiolas >> <chrmargiolas at gmail.com> wrote: >> > Hello, >> > >> > Thank you a lot for the feedback. I believe

Hi Sergos and Samuel, Thanks for the links, I've got it mostly working now. I still have a problem with linking the code. It seems that the clang driver doesn't pass its library search path to nvlink when linking the generated cuda code to the target library, resulting in it not correctly finding libtarget-nvptx.a. Is there some flag or environment variable that I should set here?

On Sat, Jun 6, 2015 at 6:24 PM, Christos Margiolas <chrmargiolas at gmail.com> wrote: > Hello, > > Thank you a lot for the feedback. I believe that the heterogeneous engine > should be strongly connected with parallelization and vectorization efforts. > Most of the accelerators are parallel architectures where having efficient > parallelization and vectorization can be

On Sun, Jun 7, 2015 at 2:34 AM, Eric Christopher <echristo at gmail.com> wrote: > > > On Sat, Jun 6, 2015 at 12:31 PM C Bergström <cbergstrom at pathscale.com> > wrote: >> >> On Sun, Jun 7, 2015 at 2:22 AM, Eric Christopher <echristo at gmail.com> >> wrote: >> > >> > >> > On Sat, Jun 6, 2015 at 5:02 AM C Bergström

On Sun, Jun 7, 2015 at 2:52 AM, Eric Christopher <echristo at gmail.com> wrote: > > > On Sat, Jun 6, 2015 at 12:43 PM C Bergström <cbergstrom at pathscale.com> > wrote: >> >> On Sun, Jun 7, 2015 at 2:34 AM, Eric Christopher <echristo at gmail.com> >> wrote: >> > >> > >> > On Sat, Jun 6, 2015 at 12:31 PM C Bergström

All, I'm needing volunteers to help moderate the sessions of the LLVM Developers' Meeting. All you need to do is introduce the speaker, make sure the speaker stays on time, and run Q&A at the end (run a microphone, select people, etc). Its a pretty easy job, but critical for our meeting to run smoothly. If you are interested in moderating, please send me your top 2 session choices.

TL;DR ----- Let's allow to merge to LLVM-IR modules for different targets (with compatible data layouts) into a single LLVM-IR module to facilitate host-device code optimizations. Wait, what? ----------- Given an offloading programming model of your choice (CUDA, HIP, SYCL, OpenMP, OpenACC, ...), the current pipeline will most likely optimize the host and the device code in isolation. This

On 7/28/20 3:03 PM, Renato Golin wrote: > On Tue, 28 Jul 2020 at 20:44, Johannes Doerfert > <johannesdoerfert at gmail.com> wrote: >> What I (tried to) describe is that you can pass an array of structs via >> a CUDA memcpy (or similar) to the device and then expect it to be >> accessible as an array of structs on the other side. I can imagine this >>

Hi, a couple of weeks ago I discussed with Peter how to improve LLVM's support for heterogeneous computing. One weakness we (and others) have seen is the absence of multi-module support in LLVM. Peter came up with a nice idea how to improve here. I would like to put this idea up for discussion. ## The problem ## LLVM-IR modules can currently only contain code for a single target

Hi Tobias, I didn't really get it. Is the idea that the same bitcode is going to be codegen'd for different architectures, or is each sub-module going to contain different bitcode? In the later case you may as well just use multiple modules, perhaps in conjunction with a scheme to store more than one module in the same file on disk as a convenience. Ciao, Duncan. > a couple of weeks

In our project we combine regular binary code and LLVM IR code for kernels, embedded as a special data symbol of ELF object. The LLVM IR for kernel existing at compile-time is preliminary, and may be optimized further during runtime (pointers analysis, polly, etc.). During application startup, runtime system builds an index of all kernels sources embedded into the executable. Host and kernel code

On 04/03/2012 03:13 PM, Hongbin Zheng wrote: > Hi Yabin, > > Instead of compile the LLVM IR to PTX asm string in a ScopPass, you > can also the improve llc/lli or create new tools to support the code > generation for Heterogeneous platforms[1], i.e. generate code for more > than one target architecture at the same time. Something like this is > not very complicated and had

On 7/28/20 2:24 PM, Renato Golin wrote: > On Tue, 28 Jul 2020 at 20:07, Johannes Doerfert via llvm-dev > <llvm-dev at lists.llvm.org> wrote: >> Long story short, I think host & device need to, and in practice do, >> agree on the data layout of the address space they use to communicate. > > You can design APIs that call functions into external hardware that

[off topic] I'm not a fan of the "reply-to-list" default. Thanks for the feedback! More below. On 7/30/20 6:01 AM, David Chisnall via llvm-dev wrote: > On 28/07/2020 07:00, Johannes Doerfert via llvm-dev wrote: >> TL;DR >> ----- >> >> Let's allow to merge to LLVM-IR modules for different targets (with >> compatible data layouts) into a single

Hello, i have been working with an accelerator backend. the accelerator has large vector/simd units. i want streaming loops (non-temporal) vectorized present in code to be offloaded to accelerator simd units. i find polly really suitable for this. i am thinking if the generated IR is passed to polly and then it analyzes loop to know it posses no reuse, if such loop is identified accelerator

On Wed, Apr 4, 2012 at 4:49 AM, Tobias Grosser <tobias at grosser.es> wrote: > On 04/03/2012 03:13 PM, Hongbin Zheng wrote: > > Hi Yabin, > > > > Instead of compile the LLVM IR to PTX asm string in a ScopPass, you > > can also the improve llc/lli or create new tools to support the code > > generation for Heterogeneous platforms[1], i.e. generate code for