similar to: [LLVMdev] how to disable sse and avx

Thanks, Mats. Actually, it is able to generate the assembly now if I use the follow command: clang++ -O3 -S -mllvm --x86-asm-syntax=intel -mno-sse -o test_nosee.s test.cpp However, when I use g++ -O3 -o test_nosse test_nosse.s -lm to generate the executable, if gives me the following errors: Error: too many memory references for `sub' Error: too many memory references for `mov' Error:

Thanks, Shahid. It is fixed now. On Fri, Apr 17, 2015 at 8:50 PM, Shahid, Asghar-ahmad < Asghar-ahmad.Shahid at amd.com> wrote: > Hi zhi, > > > > You have to also pass the value type to getDecalaration() API such as > > > > Value* sqrtv = Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_sqrt_pd, > v->getType()); > > > > Regards, > >

Thanks Nick, that's something what I am trying to implement as the following. But it seems I still only get the constant value not the instruction. Could you please go over the following instruction and see what wrong with it? Thanks for your time again. Value *vecVal = NULL; IRBuilder<> builder(&*pInst); Type *vecTy = VectorType::get(Type::getDoubleTy(ctxt), 2); Value

I got it. Thanks, Nick. So, it is back to the previous problem. If I have the following instruction: %3 = fadd double %1, double %2 I want to change it into %6 = fadd <2 x double> %4, double %5 where %4 = <double %1, double %1>, %5 = <double %2, double %2>, how can I do this? Thanks, Best On Fri, Apr 17, 2015 at 1:56 AM, Nick Lewycky <nicholas at mxc.ca> wrote: >

It seems that the problem was because I used builder.CreateFAdd to create a <2 x double> vectortype FADD instruction. It works if I use it to create the scalar version FADD. I want to have an instruction like: *%2 = fadd <2 x double> undef, <2 x double> undef. *The following is the way I used to create the vectorized FADD instruction: //pInst is a double type instruction

I see. My CPU is a general Core i7 Ivy bridge CPU. On Fri, Apr 10, 2015 at 6:48 PM, Bruce Hoult <bruce at hoult.org> wrote: > I suppose that depends on your CPU. Do you even have a CPU that supports > operations on <N x i1> as packed bits in vector registers? > > > On Sat, Apr 11, 2015 at 12:43 PM, zhi chen <zchenhn at gmail.com> wrote: > >> Yes, but my

Does the insert point also mean inserting before the instruction? On Tue, Apr 21, 2015 at 3:36 PM, Daniel Berlin <dberlin at dberlin.org> wrote: > IRBuilder takes an insertion point. > Use it? > > > On Tue, Apr 21, 2015 at 3:17 PM, zhi chen <zchenhn at gmail.com> wrote: > > The current instruction is: > > > > Instruction *pInst; > > > >

Value * is the instruction. use dyn_cast<Instruction> to get to it. On Thu, Apr 16, 2015 at 11:39 PM zhi chen <zchenhn at gmail.com> wrote: > But IRBuilder.CreateXYZ only returns a "VALUE" type. Can I get the > instruction created by it? For example, > > IRBuilder<> builder(&*pinst); > Value *val = builder.CreateFAdd(LV, RV, ""); >

If I'm understanding correctly, you're saying that vgather* is slow on all of Excavator, Haswell, Broadwell, and Skylake (client). Therefore, we will not generate it for any of those machines. Even if that's true, we should not define "gatherIsSlow()" as "hasAVX2() && !hasAVX512()". It could break for some hypothetical future processor that manages to

Got it. Thanks. I will try it with the trunk version. On Wed, Jan 20, 2016 at 1:36 PM, Tim Northover <t.p.northover at gmail.com> wrote: > Hi Zhi, > On 20 January 2016 at 13:33, zhi chen <zchenhn at gmail.com> wrote: > > Thanks for your response. The attached is the .bc file after my pass. I > > could generate the assembly with -mcpu=skx but not with

Yes, but my point is that there would be some overhead to do cast the <N x i1> vectortype to an integerNty. Is there any good way to check not all of these N bits in the vectortype are 0s? On Fri, Apr 10, 2015 at 5:37 PM, Bruce Hoult <bruce at hoult.org> wrote: > Sure, if you actually just want an i1 saying whether or not at least one > bit is set to 1, then comparing against 0

It seems that http://reviews.llvm.org/D15690 only implemented gather/scatter for AVX-512, but not for AVX/AVX2. Is there any plan to enable gather for AVX/2? Thanks. Best, Zhi On Thu, Feb 25, 2016 at 8:28 AM, Sanjay Patel <spatel at rotateright.com> wrote: > I don't think gather has been enabled for AVX2 as of r261875. > Masked load/store were enabled for AVX with: >

Say if we have 8 cores, I want to get which core is running the current program. Thanks. On Thu, Nov 19, 2015 at 3:37 PM, Hal Finkel <hfinkel at anl.gov> wrote: > ----- Original Message ----- > > From: "zhi chen" <zchenhn at gmail.com> > > To: "Hal Finkel" <hfinkel at anl.gov> > > Cc: llvm-dev at lists.llvm.org > > Sent: Thursday,

That makes great sense. It would be great if we have profitability mode to see the necessity to use gathers. Or it also would be good if there is a compiler option for the users to enable LLVM to generate the gather instructions no matter it is faster or slow. Best, Zhi On Fri, Feb 26, 2016 at 12:49 PM, Sanjay Patel <spatel at rotateright.com> wrote: > If I'm understanding

So, you need to bitcast `pinst` to a pointer to Vector of double, since it (I hope for your sake) is a pointer to integer. What you are trying to do is bitcast a pointer into a vector, which probably will lead to an assert or "bad code that doesn't work". -- Mats On 15 April 2015 at 21:57, zhi chen <zchenhn at gmail.com> wrote: > What I want to do is to change the pInst

Thanks, Bruce. So, what is the easiest way to check if there is any bit set to 1 in a <N x i1> vector type? I used bitcast instruction to cast it into "iN" first and them compare iN to 0. Do you have a better way to do it? Thanks again. On Fri, Apr 10, 2015 at 5:22 PM, Bruce Hoult <bruce at hoult.org> wrote: > LLVM doesn't have a "logical neg" (or

Yes, masked load/store/gather/scatter are completed. - Elena From: zhi chen [mailto:zchenhn at gmail.com] Sent: Thursday, February 25, 2016 01:20 To: Demikhovsky, Elena <elena.demikhovsky at intel.com> Cc: Sanjay Patel <spatel at rotateright.com>; Nema, Ashutosh <Ashutosh.Nema at amd.com>; llvm-dev <llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] how to

No. Gather operation is slow on AVX2 processors. - Elena From: zhi chen [mailto:zchenhn at gmail.com] Sent: Thursday, February 25, 2016 20:48 To: Sanjay Patel <spatel at rotateright.com> Cc: Demikhovsky, Elena <elena.demikhovsky at intel.com>; Nema, Ashutosh <Ashutosh.Nema at amd.com>; llvm-dev <llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] how to force

Does anyone know how to instrument *double* to <2 x doulbe>**, e.g., 2.2 --> <2.2, 2.2>? For example, I want to change the following IR code %arrayidx1 = getelementptr inbounds [100 x double]* @main.B, i32 0, i32 %i.021 %1 = load double* %arrayidx1, align 4, !tbaa !0 to: %arrayidx1 = getelementptr inbounds [100 x double]* @main.B, i32 0, i32 %i.021 %1 = bitcast double* %arrayidx1

The current instruction is: Instruction *pInst; How can I create a new instruction, say add, after pInst? Thanks, Zhi -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150421/8f75a4a0/attachment.html>