similar to: [LLVMdev] convert LLVM IR to another IR without SSA

Hi, Diego, Thanks for your quick reply. Inserting a copy instruction may not work here because I have a limitation of virtual register number. I need to assign registers with ssa form to registers without ssa form. I will look the source code you point out. Thanks Xiangyang On Fri, Apr 24, 2015 at 4:19 PM, Diego Novillo <dnovillo at google.com> wrote: > > > On Fri, Apr 24, 2015

Hi, Assume I have the following code. The first four instructions in each BB does the same thing. So I think GVN() can remove the redundant code. However, after I apply GVN to my module by "Passes.add(createGVNPass())" and "Passes.run(*myModule)". It seems GVN does not remove the redundant instructions. Can anyone give me a hint what's going on here? Any hint is

Thanks for your point that out. I just add DataLayout in my code such as "mod->setDataLayout("e-m:e-i64:64-f80:128-n8:16:32:64-S128");", still no luck. I'm really confused about this. Do I need to add more passes before -loop-unroll? On Sat, Aug 22, 2015 at 11:36 AM, Mehdi Amini <mehdi.amini at apple.com> wrote: > > On Aug 22, 2015, at 7:27 AM, Xiangyang

Hi, I just tried llvm-3.8 (LLVM SVN Repository). With this version, -fno-rtti can help me to compile my code and -irce can help me to do a better job for loop unrolling. However, I still have one question. If I use Clang to compile a piece of c++ code to .bc and then use 'opt -loop-rotate -loop-unroll -irce', I can get what I want. I mean, there is no conditional branch at the end of each

There's been some recent noise on the mailing list about requiring -fno-rtti; http://lists.llvm.org/pipermail/llvm-dev/2015-August/089010.html Could that be it? On Sat, Aug 22, 2015 at 12:21 AM, Xiangyang Guo via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Hi, James and Philip, Thanks for your help. > > Based on your advice, I downloaded llvm-3.7. However, with this new

Hi, Mehdi, For example, I have this very simple source code: void foo( int n, int array_x[]) { for (int i=0; i < n; i++) array_x[i] = i; } After I use "clang -emit-llvm -o bc_from_clang.bc -c try.cc", I get bc_from_clang.bc. With my code (using LLVM IRbuilder API), I get bc_from_api.bc. Attachment please find thse two files. I also past the IR here.

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Hi, All, I want to lower 64 Bits constant such as 'long' and 'double'. So I define them like this: def CONSTI64 : InstFOO<(outs GRWideRegs:$dst), (ins i64imm:$src), "const-long $dst, $src", [(set (i64 GRWideRegs:$dst), imm:$src)]>{ let isMoveImm = 1; } def CONSTF64 : InstFOO<(outs

On 1 December 2015 at 12:33, Xiangyang Guo via llvm-dev <llvm-dev at lists.llvm.org> wrote: > if I have the following IR, LICM doesn't work again, even if I use > '-loop-rotate' firstly. In this IR, the return value of intrinsic function > "foo" is used by another function "func2" as parameter. However, for the > intrinsic function

I am experimenting with LLVM optimizer and found that the bit code file clang emits is already in SSA form, but I want to generate it in non-SSA form. Would you let me know if there is any way of doing it? Cheera,Amruth -------------- next part -------------- An HTML attachment was scrubbed... URL:

On 3/29/11 12:26 PM, George Baah wrote: > Hi All, > When I run the following command > llvm-gcc -03 -emit-llvm test.cpp -c -o test.bc or llvm-gcc -emit-llvm > test.cpp -c -o test.bc > > on the program test.cpp, the IR representation is not in SSA form. > I do not see any phi functions. Actually, it is in SSA form (or more precisely, the virtual registers are in SSA form;

Hi All, When I run the following command llvm-gcc -03 -emit-llvm test.cpp -c -o test.bc or llvm-gcc -emit-llvm test.cpp -c -o test.bc on the program test.cpp, the IR representation is not in SSA form. I do not see any phi functions. program: test.cpp int main(int argc, char **argv) { int a[2],i,j; for(i=0;i<2;i++) { a[i] = i; } return a[1]; } Any clarifications will be

Hi Amruth, If you do not specify any optimization flag for 'clang' and do not run 'opt -mem2reg' pass on the generated IR file, it is in non-SSA form. However, many variables stay in memory instead of registers in this case. Thanks, Jiesheng On Wed, Jun 13, 2012 at 1:17 PM, <amruth.rd at knights.ucf.edu> wrote: > I am experimenting with LLVM optimizer and found that

Well, it *is* in SSA form, but it "cheats" by keeping values in memory. --Sean Silva On Wed, Jun 13, 2012 at 2:00 PM, Jiesheng Wei <jwei at ece.ubc.ca> wrote: > Hi Amruth, > > If you do not specify any optimization flag for 'clang' and do not run > 'opt -mem2reg' pass on the generated IR file, it is in non-SSA form. > However, many variables stay

Thanks for your reply, escha, Yes, -loop-rorate makes it work. Regards, Xiangyang 2015-12-01 12:48 GMT-05:00 <escha at apple.com>: > > > On Dec 1, 2015, at 9:30 AM, Xiangyang Guo via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > > > Hi, All, > > > > Suppose I define one memory read only intrinsic function "foo" in >

Hi, When I define an intrinsic function with memory write permission, my assumption is that we can either attach [IntrReadWriteArgMem] or [] to the intrinsic function. Based on the comment of the source code , "IntrReadWriteArgMem - This intrinsic reads and writes only from memory that one of its arguments points to, but may access an unspecified amount." "If no property is set,

Hi, Assume I define registers R0...R15 and two register classes RegA and RegB. RegA contains R0 to R7 while RegB contains R0 to R15. Then I check the machine instruction, it seems that in some cases, the %vreg0 belongs to RegB; in other cases %vreg1 belongs to RegA_RegB. Can you tell me how TableGen decides which is which? At first, I guess &verg0 will be assigned by R8 to R15 only so that

Hi, I'm using LLVM-3.8 (current SVN version) to optimize my code. After loop unrolling, I find there is 'undef' in the IR. For example, "*%.lcssa21.unr = phi double [ undef, %.lr.ph9 ], [ %13, %7 ]*". I have two questions: (1) Why this 'undef' is generated? Because before 'loop unrolling', there is no such 'undef'. (2) How LLVM backend deals with

Hi, All, Suppose I define one memory read only intrinsic function "foo" in Intrinsics.td like this def int_foo : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrReadMem]>; Suppose I have the following IR, which means the intrinsic function "foo" is called 10 times in a loop. Since the parameters of function "foo" are invariant and the function

Thanks for your reply, Philip. You are right, when I use LLVM-3.8, the 'argmemonly' shows up. Previously, I use LLVM-3.7. I think idempotent is what I want. Can you tell me how to add idempotent attribute to the function? Thanks. Regards, Xiangyang 2016-03-24 14:30 GMT-07:00 Philip Reames <listmail at philipreames.com>: > > > On 03/24/2016 12:45 PM, Xiangyang Guo via