similar to: [LLVMdev] [RFC] Project for GSoC: Unit/Regression testing for CodeGen

On 05/26/2017 03:02 PM, Matthias Braun wrote: > >> Regarding SDAG, and given that poison is already there, we would need >> to adopt a similar solution to the IR. Maybe right now we can get >> away with it because nsw is not exploited significantly (as you say). >> Just because there’s no explicit poison in SDAG, just having nsw is >> sufficient to cause

Hello LLVM, In DAGCombiner.cpp, MergeConsecutiveStores uses int64_t ElementSizeBytes = MemVT.getSizeInBits()/8; https://github.com/llvm-mirror/llvm/blob/master/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L10669 which is broken for i1 types where getSizeInBits() == 1. My out-of-tree target hits this case and eventually LLVM asserts in Type.cpp. Is there some reason MergeConsecutiveStores should

On Fri, Jan 11, 2013 at 1:08 PM, Andrew Booker <andrew.booker at arm.com>wrote: > The fmuladd intrinsic is described as saying that a multiply and > addition sequence can be fused into an fma instruction "if the code > generator determines that the fused expression would be legal and > efficient". (http://llvm.org/docs/LangRef.html#llvm-fma-intrinsic) > >

On Feb 7, 2012, at 12:10 PM, Hal Finkel wrote: >>> 1. "Target Data" for vectorization - I think that in order to improve >>> the vectorization quality, the vectorizer will need more information >>> about the target. This information could be provided in the form of a >>> kind of extended target data. This extended target data might contain:

Peter, Thanks! Do you happen to know where this needs to be changed in clang or LLVM. The code that actually interprets the constraints, generically, is in CodeGen/SelectionDAG/TargetLowering.cpp, is clang relying on that code, or is there some frontend code in clang itself that is failing to initially interpret the string? If it is the code in TargetLowering, then I don't see any support

Regarding the patches, there are two concerns AFAICT: 1. It’s a new instruction and as usual when introducing a new instruction it will require work for some time until most optimizations know about it, and to get rid of any potential perf regression. No big deal; we just need to do the work (and we have already done some of it). 2. The patch was written by a student, which may not have time to

I mean an llvm Pass that transforms switch statements into if statements. For example, if I have code with switch statements then running the pass will convert all switches to ifs in the bytecode. George On Mon, May 6, 2013 at 4:20 PM, Hal Finkel <hfinkel at anl.gov> wrote: > ----- Original Message ----- > > From: "George Baah" <georgebaah at gmail.com> > >

On Mon, 2012-02-06 at 14:26 -0800, Chris Lattner wrote: > On Feb 2, 2012, at 7:56 PM, Hal Finkel wrote: > > As some of you may know, I committed my basic-block autovectorization > > pass a few days ago. I encourage anyone interested to try it out (pass > > -vectorize to opt or -mllvm -vectorize to clang) and provide feedback. > > Especially in combination with

On Mon, Oct 28, 2013 at 10:09 AM, James Courtier-Dutton <james.dutton at gmail.com> wrote: > My guess is that this is a missed optimization, but in real life, all > projects i have worked fix this in the C or C++ code using macros that > change what instructions are used based on target platform and its > endedness. One reason for writing code like this, i.e. explicitly spelling

----- Original Message ----- > From: "Cameron McInally" <cameron.mcinally at nyu.edu> > To: "Andrew Booker" <andrew.booker at arm.com> > Cc: llvmdev at cs.uiuc.edu > Sent: Friday, January 11, 2013 12:37:07 PM > Subject: Re: [LLVMdev] Documentation of fmuladd intrinsic > > > On Fri, Jan 11, 2013 at 1:08 PM, Andrew Booker < >

----- Original Message ----- > From: "Duncan P. N. Exon Smith" <dexonsmith at apple.com> > To: "Chandler Carruth" <chandlerc at google.com> > Cc: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu> > Sent: Wednesday, May 27, 2015 12:59:23 PM > Subject: Re: [LLVMdev] RFC: Separate machine IR from lib/CodeGen into lib/MIR > >

> On Jan 23, 2017, at 12:36, Friedman, Eli via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > On 1/23/2017 5:21 AM, Jonas Paulsson wrote: >> Hi Eli, >> >> I would like to clarify generally what the difference is between returning SDValue() and Op (input argument unchanged) from LowerOperation()? >> >> My understanding is that returning SDValue()

Hal Finkel <hfinkel at anl.gov> writes: > There are a few conditions that contribute to the decision of whether > or not to make the fmuladd -> fma translation. The relevant code is in > CodeGen/SelectionDAG/SelectionDAGBuilder.cpp: > > case Intrinsic::fmuladd: { > EVT VT = TLI.getValueType(I.getType()); > if (TM.Options.AllowFPOpFusion !=

On Fri, 2012-04-27 at 20:30 -0500, Hal Finkel wrote: > Thanks! Do you happen to know where this needs to be changed in clang > or LLVM. The code that actually interprets the constraints, > generically, is in CodeGen/SelectionDAG/TargetLowering.cpp, is clang > relying on that code, or is there some frontend code in clang itself > that is failing to initially interpret the string? If

On 29 June 2012 23:40, Hal Finkel <hfinkel at anl.gov> wrote: > This seems like yet-another place where target-information integration > would be helpful (and, indeed, should be used). Indeed! And it's part of the plan, to make sure we get it right. However, since all folding will eventually be moved to the function pass, that's gotta be coded (if not there yet) on the pass. I

I wrote up this optimization as an LLVM IR pass last month, actually: https://code.google.com/p/foster/source/browse/compiler/llvm/passes/BitcastLoadRecognizer.cpp It recognizes trees of `or' operations where the leaves are (buf[v+c] << c * sizeof(buf[0])). There are a few improvements needed to make it fit for general consumption; it assumes (without checking) that it's targeting

Hello, Working on my (currently out-of-tree) BG/Q PPC enhancements, I've run into the following problem with vector type legalization. Here's a quick example: Scalarize node result 0: 0x2348420: v1f32 = extract_subvector 0x23434a0, 0x2348320 [ID=0] Scalarize node result 0: 0x2348220: v1f32 = extract_subvector 0x23434a0, 0x23466e0 [ID=0] Split node result: 0x23469e0: v4f32 =

Hi All, Is there a pass in llvm that converts switch statements to if statements? George -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130506/f06741c4/attachment.html>

Hi Hal, Our Architecture has indirect move instruction which increments the pointer implicitly and the target only has i8 type values. So the load of i16 will be converted to two i8 target loads wherein after the first load instruction, the pointer to the first i8 address will automatically increment to point to the next i8 value. So the post increment nature is in the Target. A normal

----- Original Message ----- > On Mon, Oct 28, 2013 at 10:09 AM, James Courtier-Dutton > <james.dutton at gmail.com> wrote: > > My guess is that this is a missed optimization, but in real life, > > all > > projects i have worked fix this in the C or C++ code using macros > > that > > change what instructions are used based on target platform and its >