similar to: [LLVMdev] Use the IR information to modify the AST

Also you might need to check use PostRASchedulerList or PostMachineScheduler, PostRASchedulerList is considered deprecated as mentioned in [1]. [1] http://lists.llvm.org/pipermail/llvm-dev/2017-April/112348.html HTH, chenwj 2017-06-10 4:03 GMT+08:00 陳韋任 <chenwj.cs97g at g2.nctu.edu.tw>: > Not saying I am totally understand how thing works, but I think you're > misleading >

Thanks :) From: 陳韋任 [mailto:chenwj.cs97g at g2.nctu.edu.tw] Sent: 14 April 2017 12:53 To: Martin J. O'Riordan <martin.oriordan at movidius.com> Cc: LLVM Developers <llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] Options for timing passes in LLVM? Refer to `llc` document [1], it would be `--time-passes`. [1] http://llvm.org/docs/CommandGuide/llc.html HTH,

Hi Bekket, I don't see any use case in the codebase adding clEnumValEnd at the end of list (for example, [1]), I also don't see there is clEnumValEnd. Do I miss something here? [1] http://llvm.org/doxygen/DwarfDebug_8cpp_source.html Regards, chenwj 2017-06-06 9:53 GMT+08:00 Bekket McClane via llvm-dev < llvm-dev at lists.llvm.org>: > Hi, > > Can anyone help reviewing

Hello, I have followed steps given in - https://stackoverflow.com/questions/29910051/integrating-llvm-passes/48142693#48142693 <https://stackoverflow.com/questions/29910051/integrating-llvm-passes/48142693#48142693>, to integrate my pass with pass manager and run it with clang. I am able to run my pass with opt - opt -mypass but when I try to run it with clang, I always get an error -

Hi weiren, Thanks for your suggestion! Yes, I am trying to do this "nested flattening". It seems that I need a post-dominator tree-based algorithm to flatten the nested loops from the innermost to the outermost, level by level. Is there any feature already existed in LLVM tools? Or similar? On Sun, Oct 22, 2017 at 2:31 AM, 陳韋任 <chenwj.cs97g at g2.nctu.edu.tw> wrote: > If

Sorry for the off topic. When I login my Phabricator account, I see there is alarm saying "Account Setup Issue: Primary Email Unverified". I cannot see where to ask Phabricator send verification mail to my primary email address. Could you help me out? :-) Thanks. Regards, chenwj 2017-04-24 18:35 GMT+08:00 Eric Liu via cfe-dev <cfe-dev at lists.llvm.org>: > It's working

Thanks. That is good suggestion. I will start to work on 4.0 now. It would be good to know the 4.0.x patch release schedule and how to contribute. I found this email containing backporting timeline for 4.0.1 (already done): http://lists.llvm.org/pipermail/llvm-dev/2017-March/111530.html >From email, it is not clear to me whether we have upcoming 4.0.2 or not. Thanks! Yonghong On Fri, Jul

The debug information is actually still in a different format in the .bc file, it is LLVM metadata. I think the best reference for it is here: https://llvm.org/docs/SourceLevelDebugging.html#ccxx-frontend You can dump it just by disassembling the .bc file to textual IR using llvm-dis and examining the !DI* metadata nodes. You will have to run the file through llc to generate an object file to

Hi, Matthias. >From the class hierarchy, ScheduleDAGMILive is also a ScheduleDAGMI. I am wondering if there will be any problem if we use subclass of ScheduleDAGMILive as post-RA scheduler? The best case is ScheduleDAGMILive just waste time on book-keeping register pressure, but I am not sure if we can still do those book-keeping after RA. Talk about post-RA scheduler, I see there is another

> > Of course, you want to duplicate as little of the generic scheduling logic > as you can. So I think the challenge is how to expose the > generic scheduler's functionality as a base class or composition of > utilities so that defining your strategy doesn't require too much > copy-paste. ​Isn't GCNMaxOccupancySchedStrategy [1] already an example on using

2018-01-16 21:03 GMT+08:00 Tim Northover <t.p.northover at gmail.com>: > On 16 January 2018 at 12:23, 陳韋任 <chenwj.cs97g at g2.nctu.edu.tw> wrote: > > Do we have to emit directives in the epilogue, too? One of my test case > fail > > due to the directives in the epilogue have been executed. After removing > > them from epilogue, the exception is caught as

Thank You Chen ! On Thu, Jun 22, 2017 at 5:21 PM 陳韋任 <chenwj.cs97g at g2.nctu.edu.tw> wrote: > Perhaps you can refer to [1]. Function name should be a global one. > > [1] http://llvm.org/docs/LangRef.html#identifiers > > HTH, > chenwj > > > 2017-06-22 16:35 GMT+08:00 SANJAY SRIVALLABH SINGAPURAM via llvm-dev < > llvm-dev at lists.llvm.org>: > >>

Hello This link didn't work for me. As I am getting error whose meaning is - there are no options as -arch i386 -arch x86_64. How should I remove this error? On Wed, Mar 22, 2017 at 6:11 PM, 陳韋任 <chenwj.cs97g at g2.nctu.edu.tw> wrote: > Hi Aayushi, > > Seems the link [1] answers your question. > > [1] http://stackoverflow.com/questions/28640585/build- >

Just use Unix IO redirect? `llc -mllvm -print-after-all &> a.txt` 2017-10-22 14:17 GMT+08:00 Dipanjan Das via llvm-dev < llvm-dev at lists.llvm.org>: > > Seems like "-mllvm -print-after-all" does the trick. Is there any switch > that dumps the output to a file instead of console? > > On 21 October 2017 at 21:33, Dipanjan Das <mail.dipanjan.das at

You can also `-disable-verify -o <output-filename> ` which will disable the verify check. On Sat, 21 Oct 2017 at 23:54 Dipanjan Das via llvm-dev < llvm-dev at lists.llvm.org> wrote: > > Yes, that definitely works. Wanted to know if there's a switch for file > output or not. > > On 21 October 2017 at 23:45, 陳韋任 <chenwj.cs97g at g2.nctu.edu.tw> wrote: >

Hi, I wonder whether the current version of LLVM supports separate compilation and linking of device code, i.e., is there a flag analogous to nvcc's --relocatable-device-code flag? If not, is there any plan to support this? Thanks! Yuanfeng Peng -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hi Andrew I am newbie. There are many headers and classes, I do not know how to use to add dwarf info to bc file. Can you show me the demo or example, is there any info about how to use these classes step by step. BR Owen 发件人: Andrew Kelley [mailto:superjoe30 at gmail.com] 发送时间: 2017年11月15日 12:51 收件人: Wuweijia <wuweijia at huawei.com> 抄送: 陳韋任

OK. About the error it’s a long story, so it’s probably better to pin some source code here. Below is a piece of code related to my problem, clipped from lib/Transforms/Utils/ValueMapper.cpp. I was wondering what “materialized” means here. Value *Mapper::mapBlockAddress(const BlockAddress &BA) { Function *F = cast<Function>(mapValue(BA.getFunction())); // F may not have

Hi All, The description of ScheduleDAGMILive [1] says: ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while updating LiveIntervals and tracking regpressure. Does the live interval and register pressure part of ScheduleDAGMILive mean the subclass of ScheduleDAGMILive is a pre-RA scheduler? I assume the post-RA scheduler no need to take

Hi All, One thing I believe also bothers someone else. Say we have the following code snippet: bits<32> insnEncoding; let insnEncoding{15-12} = 0b0100; Can we write the let expression with range list like this, with the same meaning? let insnEncoding{12-15} = 0b0100; I take a look on TGParser::ParseRangePiece (lib/TableGen/TGParser.cpp), seems the answer is YES. Can anyone