similar to: [LLVMdev] [RFC] [ARM] v6m: Suggestions for a slightly different set of default optimizer settings.

Hello, as a newbee, I'd appreciate some support on regression test setup. Specifically, I am interrested in the feature of tail call optimizations for the ARM v6m targets. This feature currently seems to be completely deactivated at the moment (v6m being based on thumb1 ?!). According to my code-reading, this feature will involve some modifications in epilogue generation. My work on a gcc

> > $ qemu-arm -cpu ? > > Available CPUs: > > arm926 arm946 arm1026 arm1136 arm1136-r2 arm1176 arm11mpcore > > cortex-m3 > > cortex-a8 > > cortex-a8-r2 cortex-a9 cortex-a15 ti925t pxa250 sa1100 sa1110 > pxa255 pxa260 > > pxa261 pxa262 pxa270 pxa270-a0 pxa270-a1 pxa270-b0 pxa270-b1 xa270- > c0 > > pxa270-c5 any > > >

On 18 December 2014 at 04:02, Tim Northover <t.p.northover at gmail.com> wrote: >> You have some special version of qemu? My default distribution's qemu >> package did not have a cortex-M0 nor has qemu head freshly taken from git: > > The trouble with Cortex-M0 (from a virtualised testing perspective) is > that it doesn't have an MMU, so any "real"

On 12/16/14 3:53 AM, Kristof Beyls wrote: > I've been wondering too about how to get better ARM v6m compile-and-execute > testing going. > > As you say Jon, the non-execution-based regression tests are surprisingly > good at catching issues; but they're no full substitute for executing the > code produced by the backend for a reasonably-sized test suite. > > If

Hello, find enclosed a first patch for adding tail call optimizations for thumb1 targets. I assume that this list is the right place for publishing patches for review? Since this is my first proposal for LLVM, I'd very much appreciate your feedback. What the patch is meant to do: For Tail calls identified during DAG generation, the target address will be loaded into a register by use

Hello Sjoerd, Thank you for your response! I was not aware that -Oz is a closer equivalent to GCC's -Os. I tried -Oz when compiling with clang and confirmed that the Clang's generated assembly is equivalent to GCC for the code snippet I posted above. clang --target=armv6m-none-eabi -Oz -fomit-frame-pointer memcpy_alt1: push {r4, lr} movs r3, #0 .LBB0_1: cmp

Hi all, I've been doing a ton of embedded work (bare metal ARM Cortex M0+ and M4, hopefully RISCV in the future) in the last year and would love to start using and hacking on the llvm toolchain. I've tried setting up clang + lld but can't get lld to work because clang tries to launch gcc. I realize support is early but I'd love to have a dev setup so I can help fix things. Could

Hi Jan, For Cortex-M0, you should probably use the armv6m string in the target triple. For M3 and M4 you need to use the thumbv7m arch string, -mthumb won't be necessary. Amara On 11 October 2013 19:23, Jan Hoogerbrugge < jan.hoogerbrugge at biface-tools.com> wrote: > Hi, > > I am trying to cross compile code for ARM Cortex m0, m3, and m4. > > For m0, I use: > >

Hi, I am trying to cross compile code for ARM Cortex m0, m3, and m4. For m0, I use: -target armv6--eabi -mcpu=cortex-m0 That seems to work. For m3 and m4, I use the following which does not work (fatal error: error in backend: CPU: 'cortex-m3' does not support ARM mode): -target armv7m--eabi -mcpu=cortex-m3 and -target armv7em--eabi -mcpu=cortex-m4 Who can help me with the

On Oct 14, 2013, at 3:27 AM, Zakk <zakk0610 at gmail.com> wrote: > Hi all, > I meet this problem when compiling the TREAM benchmark (http://www.cs.virginia.edu/stream/FTP/Code/) with enable-misched > > The small function will be scheduled as good code, but if opt inline this function, the inline part will be scheduled as bad code. A bug for this is welcome. Pretty soon, I’ll

Hi all, I meet this problem when compiling the TREAM benchmark ( http://www.cs.virginia.edu/stream/FTP/Code/) with enable-misched The small function will be scheduled as good code, but if opt inline this function, the inline part will be scheduled as bad code. so I rewrite a simple code as attached link (foo.c), and compiled with two different methods: *method A:* *$clang -O3 foo.c -static -S

Hi Andy, thanks for your help!! The scheduled code by method A is same as B when using the new machine model. it's make sense, but there is the another problem, the scheduled code is badly. load/store instruction always reuse the same register Source: #define N 2000000 static double b[N], c[N]; void Scale () { double scalar = 3.0; for (int j=0;j<N;j++) b[j] =

On 16 March 2018 at 10:38, Peter Smith via llvm-dev <llvm-dev at lists.llvm.org> wrote: > On 15 March 2018 at 19:12, Friedman, Eli <efriedma at codeaurora.org> wrote: >> Having ARMv7a instructions in an ARMv4t file shouldn't be a problem: a >> function should be allowed to override the CPU attributes to generate code >> for a newer target. This is generally

Hi, I am confused about the call to isPhyRegUsed in calculateCalleeSavedRegisters: if (Fn.getRegInfo().isPhysRegUsed(Reg)) { // If the reg is modified, save it! CSI.push_back(CalleeSavedInfo(Reg)); } It seems that isPhyRegUsed returns true if the register is read or written in the function. If this is right, why do we save a register if it is only read in the function ?? I would have

Dear LLVM developers, Hello, I'm trying to find a way of cross-compiling my c code against Baremetal Cortex-M device (so target triple will be arm-none-eabi) only using LLVM/Clang, and not using anything from GNU (ld or libc). I'm doing this to know which one of LLVM/clang and GCC produces smaller flash image size because saving flash is a big deal in our projects. 1) When I just follow

On Oct 15, 2013, at 9:28 PM, Zakk <zakk0610 at gmail.com> wrote: > Hi Andy, thanks for your help!! > The scheduled code by method A is same as B when using the new machine model. > it's make sense, but there is the another problem, the scheduled code is badly. > > load/store instruction always reuse the same register I filed PR17593 with this information. However, I

Thanks for the example, that is very useful in working out the overall scope of the problem, which is now wider than I thought it was. I've put some comments inline. On 15 March 2018 at 19:12, Friedman, Eli <efriedma at codeaurora.org> wrote: > On 3/15/2018 9:43 AM, Peter Smith via llvm-dev wrote: >> >> Hello everyone, this is most likely Arm specific, but could affect

I am linking a program to be loaded in an ARM Cortex-M0+ based microcontroller. In the linker script, I have a section allocated for the stack which roughly looks like the following. .stack : { . += __stack_size__; } > ram Using the linker in the gcc arm toolchain, arm-none-eabi-ld, this section is automatically set to type NOBITS, however, when linking with version 10.0.0 of ld.lld, the

Hi Andy, I'm working on defining new machine model for my target, But I don't understand how to define the in-order machine (reservation tables) in new model. For example, if target has IF ID EX WB stages should I do: let BufferSize=0 in { def IF: ProcResource<1>; def ID: ProcResource<1>; def EX: ProcResource<1>; def WB: ProcResource<1>; } def :

Hi all, I'm interested in obtaining the cycles spend by the CPU from LLVM and i was wondering if this was possible to obtain this with the scheduling information from LLVM. (For the cortex-m0 in particular). I found the following function : getInstrLatency() in the TargetInstrInfo class. If i sum the latencies of the instructions in a basic block i suppose i will get the total cycle cost