similar to: [LLVMdev] Phabricator update

Phab is back up - it's still a little slow (the mysql database we use is doing some cleanups). On Wed Dec 10 2014 at 5:07:07 PM suyog sarda <sardask01 at gmail.com> wrote: > And i was thinking something wrong with my proxy configuration :P > > On Wed, Dec 10, 2014 at 6:47 PM, Manuel Klimek <klimek at google.com> wrote: > >> Heya, >> >> if you wonder

On Wed, Dec 10, 2014 at 2:38 PM, Jonathan Roelofs <jonathan at codesourcery.com > wrote: > I think the send-email part of phab has yet to come back up. > Yes, restarting it would be very helpful. > > > Cheers, > > Jon > > > On 12/10/14 1:59 PM, Manuel Klimek wrote: > >> Phab is back up - it's still a little slow (the mysql database we use is

Another php type problem; can you please try again. Thanks! On Thu Dec 11 2014 at 1:37:32 PM Bruno Cardoso Lopes < bruno.cardoso at gmail.com> wrote: > I'm facing the same problem. > > On Thu, Dec 11, 2014 at 10:16 AM, suyog sarda <sardask01 at gmail.com> wrote: > > Hi, > > I am facing problem while submitting patch on phab. All things go smooth > - >

Hi Manuel, Thanks for the help. Still persists for me too. Instead of waiting indefinitely, now I get this error: Unhandled Exception ("AphrontDeadlockQueryException") #1205: Lock wait timeout exceeded; try restarting transaction On Thu, Dec 11, 2014 at 11:26 AM, suyog sarda <sardask01 at gmail.com> wrote: > The problem still persist :( > > On 12/11/14, Manuel Klimek

Hi, I am facing problem while submitting patch on phab. All things go smooth - create diff, create revision, specify title and comments. However, when I try to submit the diff by clicking "save" button, it takes a lot of time and eventually times out, failing to submit the patch. Any help on this? On Thursday, December 11, 2014, Manuel Klimek <klimek at google.com> wrote: >

On Thu, Dec 11, 2014 at 1:29 AM, Manuel Klimek <klimek at google.com> wrote: > On Thu Dec 11 2014 at 2:16:00 AM Alexey Samsonov <vonosmas at gmail.com> > wrote: > >> On Wed, Dec 10, 2014 at 2:38 PM, Jonathan Roelofs < >> jonathan at codesourcery.com> wrote: >> >>> I think the send-email part of phab has yet to come back up. >>>

Heya, I'll look into it first thing tomorrow - probably a problem with the encoding settings. On Thu Dec 11 2014 at 9:17:40 PM Robinson, Paul < Paul_Robinson at playstation.sony.com> wrote: > What I'm seeing is that Phabricator emails double-space *everything* > (not just the diffs). > > --paulr > > > > *From:* cfe-dev-bounces at cs.uiuc.edu

Thanks Nadav for the info. It clears my query :) Yes its an integer ADD, and since AVX2 supports 256 bits integer arithmetic, so its cost is less than AVX1. One query though - shouldn't then the cost of integer ADD/SUB/MUL (which would be 1) be explicitly specified in AVX2 cost table? Because right now this entry is missing and cost of these operations are taken from BaseTTI (which is

Can you point me at an example? I've spot checked stuff and cannot see anything out of the ordinary... Thanks, /Manuel On Thu Dec 11 2014 at 9:17:40 PM Robinson, Paul < Paul_Robinson at playstation.sony.com> wrote: > What I'm seeing is that Phabricator emails double-space *everything* > (not just the diffs). > > --paulr > > > > *From:* cfe-dev-bounces at

On Thu Dec 11 2014 at 10:52:05 PM Duncan P. N. Exon Smith < dexonsmith at apple.com> wrote: > Manuel, I'm getting another problem: every commit I make, Phabricator > sends me an email with "[Diffusion]" in the title. This is just the > last day or so, so I figure it also has to do with the update. > Yea, that's a new feature we got with the update. You can

Hi, All, Duncan, Rafael, David, Nick. This is regarding pattern matching in InstructionCombine pass. We use 'match' functions many times, but it doesn't do the pattern matching effectively. e.x. Lets take pattern : (A ^ B) | ((B ^ C) ^ A) -> (A ^ B) | C (B ^ A) | ((B ^ C) ^ A) -> (A ^ B) | C Both the patterns above are same, since ^ is commutative in Op0. But,

Your clang invocation below works for me, and generates target triple in the llvm IR of i386. And then in the specific options for the functions it generates the following: ; Function Attrs: nounwind define float @foo() #0 { entry: ret float 1.000000e+00 } attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"= "true"

Hi all, I have a query regarding Cost Table for AVX2 in TargetTransformInfo. The table consist of entries for shift and div operations only. There are no entries for ADD, SUB and MUL for AVX2 cost table. Those entries are present in Cost Table for AVX. The reason for query is - when my sub target feature is AVX2, in SLP Vectorization, while calculating scalar cost of ADD, it doesn't see

Thanks Sean for the reference. I will go through it and see if i can implement it for generic boolean expression minimization. Regards, Suyog On Wed, Aug 13, 2014 at 2:30 AM, Sean Silva <chisophugis at gmail.com> wrote: > Re-adding the mailing list (remember to hit "reply all") > > > On Tue, Aug 12, 2014 at 9:36 AM, suyog sarda <sardask01 at gmail.com> wrote:

Hi Duncan, David, Sean. Thanks for your reply. > It'd be interesting if you could find a design that also treated these > the same: > > (B ^ A) | ((A ^ B) ^ C) -> (A ^ B) | C > (B ^ A) | ((B ^ C) ^ A) -> (A ^ B) | C > (B ^ A) | ((C ^ A) ^ B) -> (A ^ B) | C > > I.e., `^` is also associative. Agree with Duncan on including associative operation too.

Hi Suyog, Thanks for looking at this. This has recently got itself onto my TODO list too. > I am not sure how much all this will improve the code quality for horizontal reduction > (donno how frequently such pattern of horizontal reduction from same array occurs in real world/SPECS). Actually the main loop of 470.lbm can be SLP vectorized like this. We have three parts to it: A fully

Hi Arnold, Thanks for your reply. I tried test case as suggested by you. *void foo(int *a, int *sum) {*sum = a[0]+a[1]+a[2]+a[3]+a[4]+a[5]+a[6]+a[7]+a[8]+a[9]+a[10]+a[11]+a[12]+a[13]+a[14]+a[15];}* so that it has a 'store' in its IR. *IR before vectorization :*target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128" target triple =

Hi Tim, > > cortex-a15 vfpv4 : vmla instruction emitted (which is a NEON instruction) > > I get a VFP vmla here rather than a NEON one (clang -target > armv7-linux-gnueabihf -mcpu=cortex-a15): "vmla.f32 s0, s1, s2". Are > you seeing something different? > As per Renato comment above, vmla instruction is NEON instruction while vmfa is VFP instruction. Correct

Thanks Kevin for the reply. I got the point now :) On 10 Apr 2015 00:18, "Smith, Kevin B" <kevin.b.smith at intel.com> wrote: > For x86_64 ABI, a minimum feature set of SSE2 is required. > > > > Kevin > > > > *From:* llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] *On > Behalf Of *suyog sarda > *Sent:* Thursday, April 09,

Hi, Is LLVM be able to generate code for the following code? %mul = mul <2 x i32> %1, %2, where %1 and %2 are <2 x i32> type. I am running it on a Haswell processor with LLVM-3.4.2. It seems that it will generates really complicated code with vpaddq, vpmuludq, vpsllq, vpsrlq. Thanks, Zhi -------------- next part -------------- An HTML attachment was scrubbed... URL: